Senior Mixed-Signal IP Design Engineer

MediaTek is a leading global fabless semiconductor company powering more than 2 billion devices a year. Our cutting-edge system-on-chip solutions enable some of the world's most popular smartphones, smart TVs, connectivity products, IoT devices, and more. We combine deep engineering expertise with a collaborative, fast-paced work environment where innovation, curiosity, and teamwork drive everything we do.

About the Role

MediaTek is seeking a motivated Senior IP Design Engineer interested in architectural modeling and digital design for Dynamic Voltage & Frequency Scaling (DVFS) IP. In this role, you will build high-level architectural models for DVFS IP to evaluate new architectures and features; identify system-level performance bottlenecks and explore design trade-offs; develop quality digital designs using SystemVerilog RTL based on architectural specifications; conduct RTL signoff checks and collaborate with physical design teams on performance optimization. You will gain the opportunity to develop state-of-the-art power and performance management used in High-Performance Compute (HPC) products, including the design of clock delivery networks (CDN) and power delivery networks (PDN) for modern CPU/GPU/NPU.

Key Responsibilities

1. Architectural Modeling: Build high-level architectural models to evaluate new architectures, features, and design trade-offs before RTL implementation.
2. Digital Design Development: Create quality digital designs using SystemVerilog RTL that meet the computational functions or control sequences specified in the design specifications.
3. Conduct RTL sign-off checks, including LINT, CDC, & CLP.
4. Co-work with verification teams for block-level and system-level verification
5. Supply necessary collateral for physical design, including SDC/UPF, and collaborate with the physical design team for timing critical path and power analysis.