Senior Packaging Engineer Microelectronics

Kforce is partnering with an innovative and rapidly growing communications technology company seeking to hire a Senior Packaging Engineer (Microelectronics) in the Tempe, AZ area (hybrid work schedule).

Summary: This position would place you as the key Microelectronics Packaging Engineer on a talented space electronics engineering team, responsible for developing next-generation packaging solutions for advanced RF communications products supporting cutting-edge space systems.

In this role, you would lead all aspects of microelectronics packaging development, working closely with RFIC, MMIC, and module design teams to create advanced packaging solutions for devices ranging from ICs and System-in-Package (SiP) designs to complex modules and sub-assemblies.

Key areas of responsibility include:

• Developing advanced packaging architectures for RF communication products
• Defining package structures and materials to meet reliability, performance, manufacturability, and cost requirements
• Designing and developing semiconductor packages
• Driving the full package development lifecycle - package definition, stack-up, substrate layout, bond diagrams, drawings, predictive modeling, testing, and final release
• Utilizing thermal, mechanical, and electrical modeling to ensure early design success
• Leading technical engagement with external packaging vendors and manufacturing partners
• Supporting technology roadmaps and long-term packaging innovation initiatives