Senior Pre-Silicon SoC Modeling Engineer, Annapurna Labs Machine Learning Accelerators, AWS

AWSs Trainium and Inferentia chips power the worlds largest machine learning clusters. Our team builds C++ models of these custom SoCs that RTL designers, verification engineers, and software teams depend on throughout the silicon development lifecycle. Were looking for a modeling engineer to build and own models that directly impact how our chips are designed, verified, and brought to production.

What youll do:

• Build and own models of SoC subsystems - translating architecture specs and RTL behavior into accurate, testable C++ models
• Work directly with RTL design and verification teams to validate model behavior against RTL, debug discrepancies, and support pre-silicon verification flows
• Develop model-based test infrastructure: regression suites, RTL correlation checks, and coverage-driven testing
• Contribute to performance modeling efforts - building cycle-approximate models that help architects evaluate design trade-offs before RTL exists
• Improve modeling methodology and infrastructure: how models are structured, integrated, tested, and released to DV and architecture teams
• Collaborate with chip architects to understand upcoming designs and plan modeling work ahead of RTL availability

Why this role is interesting:

• Your models are used to verify silicon before its built - bugs you catch save months of schedule and millions of dollars
• Youll work at the intersection of software engineering and chip design, with deep visibility into how custom ML accelerators are architected
• As the team scales, theres a clear path into architectural modeling - using your models to influence chip design decisions, not just validate them
• Small team, high ownership, direct impact on AWSs most strategic silicon programs

You will thrive in this role if you:

• Have built functional or performance models of SoCs, ASICs, GPUs, CPUs, or IP blocks
• Are comfortable working with architectural / design specifications or reference implementations and translating them into C++ or SystemC models
• Understand verification concepts and have worked with DV teams or in pre-silicon validation environments
• Care about model fidelity and have experience correlating models against RTL or silicon
• Are interested in expanding into architectural performance modeling as the team grows
• Enjoy working on a small, high-impact team where you own significant pieces of the stack

No ML background needed. Youll learn the ML accelerator domain on the job.

This role can be based in Cupertino, CA or Austin, TX.