Senior SoC Digital Design Engineer, Multimedia Lab

About the team: Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.

Responsibilities

• Architecture Design: Participate in defining the architecture of SoC top or subsystems (NoC/CPU/NPU/ISP/Codec), and conduct PPA (Power, Performance, Area) evaluation during the early design phase.
• RTL Implementation: Write high-quality, well-structured RTL code (Verilog/SystemVerilog) and maintain related design documentation.
• Front-End Quality Control: Perform Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) checks to ensure code standard compliance and design robustness.
• Cross-Functional Collaboration: Work closely with the Verification team for debugging and achieving Coverage closure; collaborate with the Backend/Mid-end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA (Static Timing Analysis), and power optimization.
• Low Power Design: Participate in the formulation of chip low-power strategies, proficiently apply Clock Gating and Power Gating techniques, and support the UPF (Unified Power Format) flow. Minimum Qualifications:
• Bachelor's degree or higher in Microelectronics, Integrated Circuits, Computer Science, Electrical Engineering, or a related field.
• 3+ years of experience in digital front-end design (open to highly promising candidates with less experience).
• Mastery of Verilog/SystemVerilog and a solid foundation in digital circuits.
• Proficiency with mainstream front-end EDA tools (e.g., Spyglass, Design Compiler, PrimeTime).
• Fluent in at least one scripting language (Python, Perl, Tcl, Makefile) for workflow automation.

Preferred Qualifications:

• Deep understanding of NPU architecture, HW/SW co-design and AI hardware acceleration.
• Proven experience in SoC-level performance profiling and bottleneck analysis.
• Hands-on experience in the integration of complex SoC core subsystems (e.g., CPU/NPU clusters, Memory subsystems).
• Successful tape-out experience in advanced process nodes (7nm/5nm/3nm)