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Senior Staff CAD Engineer

Protingent

San Jose, CA

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JOB DETAILS
SALARY
$65–$75 Per Hour
SKILLS
Automation, Bash Scripting, CAD/CAM (Computer-Aided Design/Computer-Aided Manufacturing), Cadence, Circuit Design, Communication Skills, Computer Engineering, Computer Science, Computer Skills, Cross-Functional, Customer Support/Service, DRC Flows, Design Flows, Ecosystems, Electrical Engineering, Electricity, Electro-migration, IP (Internet Protocol), IR (Infrared), Industry Standards, Information Technology & Information Systems, Integrated Circuits (ICs), LVS Flows, Linux Operating System, Mixed Signal IC Design, Perforce Source Control Management (SCM) Software, Perl Programming Language, Problem Solving Skills, Python Programming/Scripting Language, Radio Frequency, Scripting (Scripting Languages), Simulation, Source Code/Configuration Management (SCM), System-on-a-Chip (SoC), Tcl-Tk, Technical/Engineering Design, Unix Shell Programming, Vendor/Supplier Relations
LOCATION
San Jose, CA
POSTED
14 days ago
Job Title: Senior Staff CAD Engineer

Position Description: Protingent Staffing has an exciting contract Senior Staff CAD Engineer with our client located in San Jose, CA.

Job Description:
  • We are looking for a senior IC EDA/CAD Engineer to own and advance our EDA design flows, IT infrastructure, and signoff methodologies.
  • You will be the technical authority on our EDA environment, setting up and maintaining advanced FinFET PDKs (e.g., 2nm or 3nm), Cadence analog/mixed-signal design flows, and digital implementation environments.
  • You will play a critical role in ensuring first-time-right silicon by developing, deploying, and supporting industry-standard backend signoff flows across RF, Analog, High-Speed IO, and Digital SoC chips.

Job Responsibilities:
  • PDK & Environment Setup: Install, qualify, and maintain advanced foundry PDKs (2nm/3nm FinFET nodes) and manage the use of the underlying IT infrastructure, compute clusters and grid utilization, license utilization.
  • Analog/Mixed-Signal Flow Development: Establish, optimize, and support the Cadence Design Systems front-to-back design environment (Virtuoso, Innovus) tailored for RF, analog, and high-speed IO interfaces.
  • Physical Verification & Signoff: Create, automate, and maintain robust chip-level and IP signoff flows using Siemens Calibre for DRC/LVS and Synopsys StarRC for parasitic extraction.
  • Advanced Reliability Verification: Deploy and support Electro-migration/IR-drop (EMIR) simulation flows and Programmable Electrical Rule Checking (PERC) to guarantee reliability at advanced nodes.
  • Automation & Support: Develop and maintain scripts and utilities that eliminate manual toil, standardize flows across projects, and reduce tool integration friction; act as the primary interface to EDA vendors for issue escalation and roadmap alignment.

Job Qualifications:
  • Education & Experience: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 5+ years of hands-on IC CAD experience.
  • Advanced Node Expertise: Direct experience managing PDKs and signoff flows for advanced FinFET technologies (5nm, 3nm, or 2nm).
  • Tool Proficiency: Deep operational knowledge of Siemens Calibre (DRC, LVS, PERC), Synopsys StarRC, and the Cadence Virtuoso/Innovus ecosystem.
  • Scripting & Automation: Strong scripting ability in SKILL and Perl; working proficiency in Python, Tcl, and Bash/Shell for flow automation and tool integration.
  • Systems & Infrastructure: Solid command of Linux, experience with compute grid/cluster management (e.g., LSF, SGE), and version control systems (e.g., Perforce, ICManage).
Nice To Have:
  • Working knowledge of advanced node design challenges: multi-patterning, dummy fill effects, and layout-dependent effects (LDE) and DFM sign-off.
  • Background in custom layout or circuit design, allowing for deep empathy and effective collaboration with design engineers.
  • Familiarity with foundry engagement processes: design rule waiver requests, PDK issue reporting, and process qualification cycles.
  • Proactive problem-solving mindset with excellent communication skills to support a multi-disciplinary team.

Job Details:
  • Job Type: Contract
  • Pay Range: $65 - $75 an hour.
  • Location: San Jose, CA (Onsite).

Benefits Package: Protingent offers competitive salaries, insurance plan options (HDHP plan or POS plan), education/certification reimbursement, pre-tax commuter benefits, Paid Time Off (PTO), and an administered 401k plan.

About Protingent: Protingent is an Award-Winning provider of top-tier Engineering and IT talent, trusted by companies at the forefront of innovation — from Software and Aerospace to AI, Clean Tech, Medical Devices, and Connected Technologies. We’re passionate about making a positive impact by connecting exceptional talent with meaningful opportunities and helping our clients build the future.

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