Signal Integrity & Interconnect Engineer - High‑Speed Channels & mmWave Packaging

POINT2 TECHNOLOGY INC

  • San Jose, CA
  • 30+ days ago
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    Skills

    • 802.3unmatched
    • Artificial Intelligence (AI)unmatched
    • Data Modelingunmatched
    • Electrical Engineeringunmatched
    • Ethernetunmatched
    • HFSS (High Frequency Structure Simulator)unmatched
    • IEEE (Institute of Electrical and Electronic Engineers)unmatched
    • Mechanical Designunmatched
    • Mechanical Engineeringunmatched
    • Network Operations Centerunmatched
    • Oscilloscopeunmatched
    • PCI Express (PCI-E)unmatched
    • Performance Tuning/Optimizationunmatched
    • Physicsunmatched
    • Printed Circuit Board (PCB)unmatched
    • Problem Solving Skillsunmatched
    • Signal Integrityunmatched
    • Simulationunmatched
    • System Architectureunmatched
    • System Integration (SI)unmatched
    • Systems Administration/Managementunmatched
    • Team Playerunmatched

    Description

    Overview

    Design and optimize the high‑speed interconnect "highways" that enable Point2's next‑generation ultra‑high‑speed data‑center links. Work across die, package, PCB, and complex mechanical connectors to ensure flawless signal transmission at mmWave and sub‑THz frequencies. Join a fast‑paced, highly technical team where your SI expertise directly shapes system performance and product success.

    Responsibilities

    Design and model high‑speed interconnects from silicon die through package, PCB, and external connectors.

    Define system architecture for near-package and co-package e-Tube for datacenter rack backplane

    Use advanced 3D EM simulation tools (e.g., HFSS) to model vias, transitions, connectors, and complex channel structures.

    Optimize channel performance for mmWave and sub‑THz operation, including parasitics, coupling, and EM behavior.

    Perform post‑fabrication lab validation using VNAs, TDRs, high‑speed oscilloscopes, and BERTs.

    Correlate simulation results with measured data and refine models for accuracy and performance.

    Collaborate closely with RFIC designers, mechanical engineers, and system architects on co‑design and integration.

    Contribute to design reviews, architecture discussions, and system‑level SI strategy.

    Qualifications

    • Ph.D. in Electrical Engineering, Physics, or related field, or M.S. with 3+ years of relevant industry experience.
    • Extensive hands‑on experience with 3D EM simulation for SI/PI modeling of PCB interconnects, vias, and connectors.
    • Experience with data center AI cluster scale-up architecture, system configuration, connectivity technologies, and SI models
    • Standards knowledge with Ethernet, PCIe, NVLink, UALink, IEEE 802.3xx
    • Strong background in high‑frequency lab measurements and model‑to‑hardware correlation.
    • Excellent problem‑solving, communication, and cross‑functional collaboration skills.

    Location(s)

    Silicon Valley, CA (San Jose metro area)

    Irvine, CA (Orange County area)

    Seoul, South Korea

    Numbers & Facts

    LocationSan Jose, CA

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