SMTS Design Verification Engineer

1000 Micron Technology

Minneapolis, MN

JOB DETAILS
SALARY
$178,000–$389,000 Per Year
SKILLS
ATE Testers, Analog Circuit Design, Artificial Intelligence (AI), Budgeting, Bug Tracking/Defect Management, Career Counseling, Centers for Disease Control and Prevention (CDC), Change Control, Code Coverage, Compensation and Benefits, Computer Engineering, Debugging Skills, Dental Insurance, Design Verification, Documentation, Electrical Engineering, Formal Verification, Functional Testing, Graphic Design, Healthcare, I2C, IP (Internet Protocol), Memory Hardware, PHY, Quality Assurance Methodology, Serial Link Design, Silicon Bringup, Simulation, Startup, Support Documentation, SystemVerilog, Technical/Engineering Design, Test Case, Test Plan/Schedule, Test Scenario, Testing, Verification Engineering, Verification Plans, Verilog Hardware Description Language, Vision Plan, Waveforms
LOCATION
Minneapolis, MN
POSTED
Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron's Interface Pathfinding team operates at the leading edge of that mission — driving performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon.As the Design Verification Engineer, you will own pre-silicon functional verification for a high-speed interface chip program. Working on a small, senior team spanning analog design, layout, silicon characterization, and digital design, you will build and execute the verification environment that gives the team confidence in the RTL before silicon is committed. This is a full-ownership DV role. You will write the DV plan, build the testbench infrastructure, develop directed and constrained-random tests, close coverage, and support the transition from simulation to post-silicon bring-up. The program integrates a fully custom analog PHY alongside soft IP functions including Error Counting, Eye Monitor control, and I2C management interface — providing a technically interesting and varied verification scope well beyond standard digital block verification. A distinctive aspect of this role is the opportunity — and expectation — to stay engaged through post-silicon bring-up. Your simulation environments, coverage models, and debug waveforms will be directly leveraged in the lab during chip characterization. This is a foundational hire for a growing program, and strong execution early is expected to lead to follow-on projects of increasing scope, team size, and verification complexity.Responsibilities DV Planning: Develop and maintain the full-chip DV plan covering all soft IP blocks and top-level integration; define coverage targets, test priorities, and sign-off criteria in alignment with the Chip Lead.Testbench Development: Build and maintain UVM/SystemVerilog verification environments for all key design blocks including I2C and register interface, PRBS-based Error Counting logic, Eye Monitor control state machine, PHY configuration and control register file (CSR / APB or equivalent), and top-level chip integration and block interconnect.Test Development: Write directed tests for corner cases and protocol compliance; develop constrained-random test scenarios with appropriate coverage models; achieve and document functional and code coverage closure.Assertion-Based Verification: Implement SystemVerilog Assertions (SVA) for critical control sequences, protocol compliance, and reset/initialization behavior in coordination with the Chip Lead.Formal Verification: Apply formal property checking (JasperGold or VC Formal) where applicable — CSR correctness, CDC properties, reset verification.Regression Management: Build and maintain regression infrastructure; triage failures, root‑cause issues to RTL or testbench, and track bug closure through the design team.Post‑Silicon Support: Provide debug waveforms, expected behavior documentation, and test vectors to support ATE development and lab bring‑up in coordination with the Lab Guru.DV Documentation: Maintain verification plan, coverage closure reports, and test methodology documentation to support program continuity and follow‑on chip development.Qualifications Basic Qualifications – BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field, 6–12 years of functional verification experience in a UVM/SystemVerilog environment, demonstrated experience building UVM testbench environments from scratch, experience verifying serial management interface blocks (I2C, SPI, APB, AHB, or equivalent), strong coverage-driven verification methodology, solid debugging skills across simulation waveforms and RTL, comfortable working on a small team with high individual ownership.Preferred Qualifications – Experience with formal property verification (JasperGold, VC Formal, or equivalent) for block-level sign-off, familiarity with PHY functional modeling or behavioral simulation, experience with real-number modeling (RNM) or Verilog‑AMS behavioral models, familiarity with PRBS pattern generation and error detection verification, post-silicon validation experience, experience developing ATE test vectors, prior experience in a small team or startup-like environment.Compensation The US base salary range that Micron Technology estimates it could pay for this full‑time position is $178,000.00 – $389,000.00 a year. Additional compensation may include benefits, bonuses and equity.Benefits Micron offers a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time‑off program and paid holidays.Equal Opportunity Employer Micron is proud to be an equal‑opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.To learn about your right to work.Micron Prohibits the use of child labour and complies with all applicable laws, rules, regulations, and other international and industry labour standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.#J-18808-Ljbffr

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1000 Micron Technology