Sr. Digital Asic Design Engineer (Teradyne, Agoura Hills, CA)

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose

At Teradyne, we develop advanced semiconductor test and automation solutions that enable the next generation of electronic technologies. Our Silicon Technology Engineering (STE) organization designs high-performance ASICs that power industry-leading semiconductor test systems used by the world's leading chip manufacturers. We foster a culture of innovation, collaboration, and continuous learning where engineers solve complex technical challenges that directly influence the future of technology.

Opportunity Overview

Teradyne's Digital ASIC Group is seeking a Senior Digital ASIC Design Engineer to join our engineering team in Agoura Hills, California. In this role, you will contribute to the architecture, design, implementation, and validation of complex digital subsystems used in next-generation mixed-signal ASICs for semiconductor test applications.

Working closely with system architects, analog designers, verification engineers, and physical design teams, you will take ownership of critical RTL design activities from concept through silicon bring-up. You will be responsible for delivering robust, high-quality digital designs that achieve performance, power, area, and reliability targets while supporting first-pass silicon success.

Required Qualifications

• BSEE required; MSEE preferred in Electrical Engineering, Computer Engineering, or a related field.

• 8+ years of digital ASIC or SoC design experience.

• Strong RTL design expertise using Verilog and/or SystemVerilog.

• Experience designing complex digital logic including:

• State machines

• FIFOs and buffering architectures

• High-speed datapaths

• Arbitration and control logic

• Clocking and reset architectures

• Solid understanding of ASIC development flows, including:

• Logic synthesis

• Static Timing Analysis (STA)

• Clock Domain Crossing (CDC)

• Timing closure

• Experience developing and integrating third-party and custom IP into large-scale ASICs or SoCs.

• Strong debugging and problem-solving skills throughout the design lifecycle.

• Proficiency with scripting and automation tools such as Python, Tcl, Perl, or Make.

Preferred Qualifications

• Experience with mixed-signal ASIC development and collaboration with analog design teams.
• Knowledge of Design-for-Test (DFT), scan insertion, and MBIST methodologies.
• Experience supporting silicon bring-up, validation, and characterization activities.
• Familiarity with UVM-based verification environments and simulation/debug tools.
• Experience working on advanced process nodes and high-performance semiconductor products.

What Will Make You Successful

• Ability to drive technical solutions in a collaborative, cross-functional environment.
• Strong communication skills and attention to detail.
• Passion for developing innovative semiconductor technology.
• Desire to continuously improve design methodologies, automation, and engineering efficiency.
• A proactive approach to problem solving and ownership of deliverables from specification through production release.

Compensation: The base salary range for this role is $154,900 - $247,800. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.

Benefits: Teradyne offers a variety of comprehensive health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details.

We are an equal-opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment.

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