Job Description
Description
Position Overview:
Work closely with design teams and CAD/EDA stakeholders to identify workflow bottlenecks across the chip development lifecycle—such as DRC/CDC/STA debug, regression triage, PPA convergence, and ECO iteration. This role focuses on building scalable data pipelines and models, and integrating AI-driven solutions into production CAD and verification flows.
Responsibilities:
- Identify and prioritize high-impact opportunities to apply AI/ML to chip design and verification workflows, spanning RTL-to-GDS, signoff, debug, and regression
- Build and maintain data pipelines to extract, normalize, and analyze signals from EDA tool logs, reports, run artifacts, and design metadata (e.g., timing reports, violations, coverage, failures)
- Develop ML models, heuristics, and analytics to improve efficiency and quality in areas such as STA, DRC/LVS, ECO optimization, and debug acceleration
- Integrate AI solutions into existing CAD infrastructure, including automation systems, regression frameworks, job schedulers, and design databases
- Collaborate with EDA vendors as needed for tool enablement, feature requests, debugging, and evaluation of vendor solutions versus internal implementations
Requirements:
- BS or MS in Electrical Engineering, Computer Science, or equivalent industry experience
- 2+ years of experience in CAD/EDA flow engineering, design automation, or a related semiconductor workflow role
- Strong programming skills, with Python required; experience with shell, Tcl, or Perl as needed
- Hands-on experience applying machine learning to real-world engineering problems
- Solid understanding of at least one major EDA workflow domain (e.g., place & route, physical layout, DRC/LVS, STA, power, CDC, DFT, simulation/regressions)
- Experience working with large-scale, noisy operational data (EDA logs and reports) and building robust automation around it
Annual base salary for this role in California, US is expected to be between $110,000 - $145,000. Actual pay will be determined by several factors such as relevant skills and experience, and the pay of employees in a similar role.
EOE/Minorities/Females/Vet/Disability
Numbers & Facts
| Location | Santa Clara, California |
| Industry | Electronics, Components, and Semiconductor Mfg |
| Salary | $110,000–$145,000 Per Year |
| Company Size | 1,500 to 1,999 employees |
| Year Founded | 1995 |
| Website | http://www.ovt.com/ |
About Company
OmniVision Technologies is a leading developer of advanced digital imaging solutions. Its award-winning CMOS imaging technology enables superior image quality in many of today’s consumer and commercial applications, including mobile phones, notebooks, tablets and webcams, digital still and video cameras, security and surveillance, entertainment devices, automotive and medical imaging systems. Find out more at www.ovt.com.
Skills
- Analysis Skillsunmatched
- Artificial Intelligence (AI)unmatched
- Automationunmatched
- Automation Systemsunmatched
- CAD/CAM (Computer-Aided Design/Computer-Aided Manufacturing)unmatched
- Centers for Disease Control and Prevention (CDC)unmatched
- Computer Programmingunmatched
- Computer Scienceunmatched
- DFT (Design for Test)unmatched
- DRC Flowsunmatched
- Data Managementunmatched
- Data Modelingunmatched
- Database Designunmatched
- Debugging Skillsunmatched
- Design Verificationunmatched
- Electrical Engineeringunmatched
- Establish Prioritiesunmatched
- Home Automationunmatched
- LVS Flowsunmatched
- Machine Learningunmatched
- Metadataunmatched
- Perl Programming Languageunmatched
- Place and Routeunmatched
- Product Lifecycleunmatched
- Python Programming/Scripting Languageunmatched
- Quality Managementunmatched
- Scalable System Developmentunmatched
- Semiconductorsunmatched
- Simulationunmatched
- Tcl-Tkunmatched
- Team Playerunmatched
- Unix Shell Programmingunmatched
- Vendor/Supplier Evaluationunmatched
- Workflow Analysisunmatched
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