Sr. PCIe PHY Validation Engineer

About the Company:

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

About the Role:

As aHigh Speed SerDes Validation Engineer, you will own the end-to-end electrical compliance and performance optimization for our enterprise SSD (eSSD) portfolio. You will lead the efforts to secure PCISIG PCIe Gen 5 (and upcoming Gen 6) Integrator List official certification. This role is critical to ensuring our high-speed SerDes architectures deliver maximum data throughput and reliability across next-generation data center servers.

Core Responsibilities: 

• Define validation goals, objectives, and metrics to ensure product performance and compliance.
• Develop and execute comprehensive test plans for SerDes interfaces (PCIe).
• Debugging and troubleshooting PHY/firmware-related issues affecting interface performance.
• Analyze test data to identify trends and issues, providing actionable insights to improve SerDes performance.
• Collaborate with cross-functional teams to resolve and optimize PHY related issues.
• Develop test automation, API, and Python script in Linux environment to perform Lane Margining Tests (LMT), collect data at failure points, and parse data for analysis. 

Minimum Qualifications:

• BS in Electrical Engineering or Computer Engineering or equivalent experience.
• Good understanding of DSP-based high-speed SERDES architectures.
• Familiarity with lab instrumentations like Oscilloscopes, BERT, TDR, VNA.
• 2-5+ years of hands-on experience with SERDES performance tuning.
• Working experiences with programming and scripting languages such as C/C++, JS and Python

Preferred Qualifications: 

• Signal and Power Integrity Knowledge.