Staff ASIC Design Engineer

AI Vision Processors For Edge Applications

Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.

Job Description

Ambarella is a leading fabless semiconductor company at the forefront of edge AI-based computer vision. Our SoCs (System-on-Chips) power everything from autonomous driving and ADAS to intelligent video security and robotics. We are building the next generation of Edge AI, operating at the intersection of high-performance hardware and real-world software deployment.

Why this is an ideal opportunity for an experienced VLSI designer:

This role offers the opportunity to work on highly differentiated SoC designs where your contributions are visible, meaningful, and directly connected to the chip being built. Unlike roles that focus on a narrow block or isolated function, this position provides broad exposure across video compression, image processing, vector computation, processor cores, memory subsystems, and flexible compute architectures for next-generation edge AI applications. Experienced VLSI designers will have the chance to influence micro-architecture, optimize RTL for performance, power, and area, participate in chip bring-up, and see their work move from concept through silicon. It is a unique opportunity to apply deep design expertise while gaining wide technical scope, strong product context, and clear ownership of impactful work in real-world AI and computer vision systems.

Position Responsibilities:

• Designing and implementing video compression, image processing, vector computation, and flexible compute systems optimized for future AI agents and large language model (LLM) inference—alongside processor cores and memory subsystems using System Verilog, with a focus on enabling next-generation edge AI markets such as automation, robotics, and intelligent low power embedded systems.
• Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages.
• Synthesize and optimize RTL for timing, area, and power.
• Explore micro-architecture and architectural tradeoffs via quick modelling using scripting languages such as python, Perl etc.
• Developing front-end methodologies and tool flows.
• Participating in chip bring-up and testing.
• Analyzing and reviewing code coverage and functional coverage and providing recommendations to the verification team to address any gaps.

Requirements:

• Master’s degree in electrical/Electronics/Computer Engineering with 5-10 years of experience.
• Good understanding of computer architecture, logic design and VLSI design.
• Knowledge of System Verilog, Verilog, python, and Perl.
• Knowledge of design verification, and functional coverage.
• Ability to program in scripting languages and the ability to write assembly language programs.
• Strong communication skills and a good team player.
• Adept problem-solving abilities
• Knowledge of logic synthesis and timing closer is a plus

The base salary range is $195,000-$226,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  We also offer new-hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits.