Technology Architect | DevOps | DevOps Architecture Consultancy

Location: San Jose, CA 95134 - need local candidates

Pay Range: 30-35/hr on w2

Should work on artech w2 

Introduction

This role requires a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints. The ideal candidate will be proficient in industry-standard SDC/STA tools and scripting for automation, excelling at identifying and resolving timing issues across all design levels.

Required Skills & Qualifications

• Bachelor’s Degree in Electrical or Computer Engineering with 6 years of ASIC or related experience or Master’s Degree in Electrical or Computer Engineering with 3 years of ASIC or related experience.
• Experience with synthesis tools (e.g., Synopsys DC/DCG/FC), STA tools such as Primetime.
• Knowledge of HDL such as Verilog/SystemVerilog programming, and scripting languages such as Shell, Perl, and strong experience scripting with TCL.
• Experience with digital design concepts (e.g., clocking, timing exceptions, and async boundaries).
• Experience with block/full chip SDC development in functional and test modes.
• Applicants must be able to work directly for Artech on W2.

Preferred Skills & Qualifications

• Effective documentation, problem-solving, and technical communication skills.
• Experience working cross-functionally and collaborating with various technical teams.
• A problem solver who loves to tackle new challenges and a self-starter who is highly motivated and thrives on innovative technology.

Day-to-Day Responsibilities

• Develop timing constraints at both block level and full-chip and validate them using industry-standard timing constraints verification tools.
• Collaborate with Front-end and Back-end teams to understand chip architecture and refine design and timing constraints for seamless physical design closure.
• Contribute to full-chip clocking design including diagrams and related documentation.

Company Benefits & Culture

• Opportunities to work on next-generation networking chips.
• Engage in a dynamic team environment.
• Encouragement for out-of-the-box thinking and innovation.

For immediate consideration please click APPLY to begin the screening process with Alex.