Seeking a Senior Physical Design Engineer with 8+ years of experience in top-level SOC implementation of complex AI and CPU designs.
Responsibilities include managing full-chip physical design, floorplanning, power grid, and clock network implementation, ensuring design closure while balancing power, performance, and area.
Ideal candidates excel in cross-disciplinary collaboration with architecture, RTL, and packaging teams, with expertise in hierarchical floorplanning, bump planning, multi-voltage domains, and physical verification.
The role offers learning opportunities in AI accelerators, chiplet integration, and advanced packaging techniques.
Hybrid location options include Santa Clara, CA; Austin, TX; or Fort Collins, CO.
Compensation ranges from $100k-$500k, based on experience and skills.
This position requires U.S. export license eligibility.
Candidates should be detail-oriented, collaborative, and thrive on complex challenges to deliver next-generation AI hardware.