Wireless Design Verification Engineer

Join Apples Wireless Connectivity team developing state-of-the-art WiFi SoCs that power hundreds of millions of Apple products worldwide. Youll be part of our vertically integrated organization shaping next-gen wireless technology from concept through production. As a Wireless Radio Verification Engineer, youll ensure first-time-right silicon success through sophisticated testbenches, comprehensive scenarios, and cutting-edge verification methodologies-enabling multi-gigabit wireless technology connecting the world! As a Wireless Radio Verification Engineer, you will be at the core of our wireless products success, leading verification of Radio digital controllers and Digital+RF subsystems that enable exceptional wireless performance. You will architect verification environments for complex radio control / transceiver paths spanning PLLs, DAC / ADC data paths, power management, and co-existence mechanisms. Working at the intersection of digital design and RF/mixed-signal-modeled systems, youll lead cross-functional collaboration spanning Design, RF, PHY, Systems, and Integration teams. Youll develop verification strategies for radio-modeled subsystems enabling robust wireless operation across diverse scenarios and environmental conditions throughout Apples product ecosystem.Lead subsystem-level verification of Radio digital controllers / data paths from test planning through feature bring up and closure. Drive cross-functional collaboration to define verification requirements and debug complex issues spanning digital and RF/analog domains. Architect sophisticated UVM testbench environments and infrastructure frameworks for radio control systems, PLL controllers, and data path subsystems. Develop constrained random scenarios for complex radio protocols and multi-domain interactions. Lead digital + mixed-signal co-simulation efforts integrating SystemVerilog behavioral and DMS models. Mentor team members on radio verification approaches and establish best practices.BS and a minimum of 10 years relevant industry experience Demonstrated expertise verifying complex digital ASICs with track record of successful silicon tapeouts. Deep knowledge of ASIC verification flows with SystemVerilog and UVM including testbench architecture, verification planning, and coverage-driven methodologies. Experience developing verification environments from scratch and bringing up complex designs in simulation. Experience with constrained random testing, functional coverage, and assertion-based verification.Experience verifying Radio digital controllers, DSPs, PLL control systems, or wireless transceiver subsystems. Exposure to RF/analog system designs such as LNAs, Mixers, PLLs, amplifiers, LDOs, DAC / ADCs. Experience with digital + mixed-signal co-simulation using SystemVerilog analog behavioral models / DMS or similar real-number-modeling approaches. Exposure to Python or similar scripting for automation, analysis, or infrastructure. Technical leadership through example-driving verification strategies, establishing best practices, and delivering complex projects. Excellent communication skills and ability to influence cross-functional technical decisions.