Design Engineer - Flow Development Broadcom IncDesign Engineer - Flow DevelopmentSan Jose, CAThe candidate must have the ability to prioritize well, communicate clearly, proactively deliver practical and quality solutions on-time, work well with external and internal partners, and possess advanced IC design engineering skills. Our group's mission is to provide an advanced timing sign-off flow to Broadcom's chip teams with the goal of achieving best in class solutions with high yield and fully optimized margins.
NVIDIA 2027 Internships: Hardware Design for Test (DFT) NVIDIA CorpNVIDIA 2027 Internships: Hardware Design for Test (DFT)Santa Clara, CACourse or internship experience related to the following areas could be required: Design for Test (DFT), Digital Design, Test Architecture and DFT Planning, Static Timing Analysis (STA), Pre-Silicon and Post-Silicon Issue Debug. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society - from gaming to robotics, self-driving cars to life-saving healthcare, climate change to virtual worlds where we can all connect and create.
Senior Digital Design Engineer NVIDIA CorpSenior Digital Design EngineerSanta Clara, CAWhat you'll be doing: As a key member of the NVLink Fusion design team, you will analyze the architectural requirements, perform the trade-off analysis for implementation, and deliver high performance, area and power efficient RTL Blocks. We have some of the most forward-thinking and hardworking people in the world working for us, and, due to outstanding growth, our special engineering teams are growing fast.
Analog/Mixed Signal Verilog Modeling Design Engineer Broadcom CorporationAnalog/Mixed Signal Verilog Modeling Design EngineerSan Jose, CAJob Description: Responsible for developing Digital-Mixed Signal (DMS) models of analog IPs such as touch controller AFEs, wireless power charging, health sensing AFE and satellite AFEs using SystemVerilog language. As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.
Digital Design Verification Engineer Broadcom CorporationDigital Design Verification EngineerSan Jose, CAAs a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. Job Description: The ideal candidate has a proven track record of working on setting up testbenches for Design Verification using UVM on large designs.
Graphics Cache Hierarchy Design Verification Engineer Apple IncGraphics Cache Hierarchy Design Verification EngineerSanta Clara, CAThe Graphics Cache Hierarchy Verification Engineer will be responsible for the pre-silicon RTL verification of graphics memory subsystem units including Caches, Memory Management Unit, Interconnects and Link interface units. You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions.
Design Verification Engineer (Silicon Engineering) SpaceXDesign Verification Engineer (Silicon Engineering)Palo Alto, CA$135,000–$155,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
Design Characterization Engineer OmnivisionDesign Characterization EngineerSanta Clara, CaliforniaWork cross‑functionally with process, applications, production, and quality teams to transition new designs into production and resolve yield, reliability, and overall product quality issues. In this role, you will characterize and optimize CMOS image sensor performance, collaborate closely across engineering disciplines, and help deliver industry‑leading sensor products with exceptional quality.
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) SpaceXSr. SOC/ASIC Physical Design Engineer (Silicon Engineering)Sunnyvale, CA$170,000–$230,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
Hardware Design & Prototyping Engineer Apple IncHardware Design & Prototyping EngineerCupertino, CA3+ years of experience with PCB design, including high speed signal routing, mixed-signal analog/digital design, and component selection. Do you deeply understand all the unique challenges of working on prototype test solutions for bleeding edge camera image sensors?.
CPU Design Timing Engineer Apple IncCPU Design Timing EngineerSanta Clara, CAWork extensively with CPU micro-architects and Implementation engineers to drive timing closure for the CPU.Minimum BS and 3+ years of relevant experience Experience with static timing analysis, noise analysis, and fixing noise in designs Experience with variation modeling Experience with TCL and either Perl or PythonPrior experience performing timing analysis in high speed digital designs such as CPUs or other similar designs Experience in a static timing analysis tool such as PrimeTime/Tempus Knowledge of physical design tools and methodology including logic synthesis, PnR, parasitic extraction, and logic equivalence Understanding of deep sub-micron technologies and scaling trends Working knowledge of CPU microarchitecture Possess data parsing, analysis and representation/plotting skills. In this role, you will be responsible for all aspects of timing including working with the implementation and RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and timing closure.
Staff ASIC Design Verification Engineer Google LLCStaff ASIC Design Verification EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing with key teams working on the development of our TPUs Vertex AI for Google Cloud Google Global Networking Data Center operations systems research and much more. Were the driving force behind Googles groundbreaking innovations empowering the development of our cutting-edge AI models delivering unparalleled computing power to global services and providing the essential platforms that enable developers to build the future.
Design Verification Engineer, Silicon GoogleDesign Verification Engineer, SiliconMountain View, CADevelop and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs using SystemVerilog Assertions (SVA). Plan the verification of complex digital design blocks by analyzing specifications and collaborating with design engineers to identify critical scenarios.
RTL Design and Integration Engineer, TPU and ML GoogleRTL Design and Integration Engineer, TPU and MLSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. In this role, you will join the team designing and developing the On-Chip Network of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in datacenters.
Sr. FPGA Design Engineer KLA CorpSr. FPGA Design EngineerMilpitas, CA$141,300–$240,200 / yearEnabling the movement towards advanced chip design, KLA''s Global Products Group (GPG), which is responsible for creating all of KLA's metrology and inspection products, is looking for the best and the brightest research scientist, software engineers, application development engineers, and senior product technology process engineers. BBP flagship products include the 29xx and 39xx series which leverage Broadband Plasma technology to capture a wide range of defects with ultimate sensitivity at the optical inspection speeds needed for inline defect monitoring.
Sr. Asic Design Verification Engineer (Silicon Engineering) Space Exploration TechnologiesSr. Asic Design Verification Engineer (Silicon Engineering)Palo Alto, CA$175,000–$280,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan.
Startup Design Accelerator (Remote) UX WomanStartup Design Accelerator (Remote)San Francisco, CARemoteTell a compelling story about users by showcasing user types, personas, stakeholder maps, journey maps, process maps, service blueprints, ideation matrixes, sketches, wireframes, UX workflows, prototypes and other visual deliverables. Lead discovery research by managing user recruitment, creating research plans, writing interview guides, leading 8-16 discovery interviews, and synthesizing interview insights.
TPU SoC Design Engineer, Cloud GoogleTPU SoC Design Engineer, CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Senior Hardware Design Engineer SambaNova Systems, Inc.Senior Hardware Design EngineerSan Jose, CA$120,000–$200,000 / yearIn this role you will take ownership of blocks within a larger subsystem - contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tapeout, and silicon bring-up. SambaNova Senior Hardware Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs deployed in our AI workload acceleration systems.
Design Verification Intern, BS - Summer 2027 MarvellDesign Verification Intern, BS - Summer 2027Santa Clara, CACompleted courses focusing on computer architecture, logic, processor, memory system, Verilog, VLSI, VHDL, UVM, analog, integrated circuit design, digital logic design, SoC/ASIC design, verification principles, signals, system and signal processing. Across all groups, you'll collaborate with your direct team and cross-functional partners (across software, physical design, digital design, and more) to deliver robust, scalable solutions that enable Marvell's leadership in data infrastructure.