Sr Principal Design Engineer CadenceSr Principal Design EngineerSan Jose, CA$154,000–$286,000 / yearYou will bridge the gap between customers, Applications Engineering (AE), Product Engineering (PE), and R&D - develop impactful customer solutions, delivering deep R&D technical support, and pioneering innovative verification methodologies to solve our customers' most complex architectural and high-Speed Protocol challenges. In this highly visible, customer-facing role, you will work directly with industry-leading semiconductor and systems companies to develop and deploy Cadence's market-leading hardware emulation and FPGA prototyping platforms.
SoC Design Verification Engineer Advanced Micro Devices, IncSoC Design Verification EngineerSan Jose, CaliforniaWhether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.
MTS Digital Design Engineer onsemiMTS Digital Design EngineerSan Jose, CAWith a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure.
FPGA Design Engineer (MTD, Tualatin, OR) Teradyne IncFPGA Design Engineer (MTD, Tualatin, OR)San Jose, CA$123,100–$196,900 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
Senior FPGA Design Engineer (MTD, San Jose, CA) Teradyne IncSenior FPGA Design Engineer (MTD, San Jose, CA)San Jose, CA$170,400–$272,600 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
Senior FPGA Design Engineer (MTD, Tualatin, OR) Teradyne IncSenior FPGA Design Engineer (MTD, Tualatin, OR)San Jose, CA$154,900–$247,800 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
Senior Static Timing Analysis (STA) Engineer Intel CorpSenior Static Timing Analysis (STA) EngineerSanta Clara, CA$164,470–$269,100 / yearYou will work across architecture, logic design, clocking, DFT, and physical design teams to ensure successful timing convergence, signal integrity, performance optimization, and product readiness. Minimum Qualifications and Experience: Bachelor's degree in Computer Engineering, Computer Science, or related STEM discipline and 6+ years of industry experience; OR a Master's degree in the same fields and 4+ years of experience.
FPGA Design Engineer (MTD, San Jose, CA) Teradyne IncFPGA Design Engineer (MTD, San Jose, CA)San Jose, CA$135,400–$216,600 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
Avionics Engineer, FPGA Cowboy SpaceAvionics Engineer, FPGASan Carlos, California$120,000–$175,000 / yearOur modular, scalable satellites collect sunlight in Low Earth Orbit to enable multiple integrated applications: transmitting energy via infrared lasers (space-to-earth and space-to-space), powering on-orbit high-performance computing clusters (GPU/TPU), and providing secure, high bandwidth optical data transport. Export Control Requirement: To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR), applicants must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.
Senior FPGA Design Engineer Anello PhotonicsSenior FPGA Design EngineerSanta Clara, CAThe ideal candidate has a strong background and can lead FPGA and hardware designs from concept through production, working closely with electrical, firmware, software, manufacturing, and test teams to deliver reliable, manufacturable products. This role requires strong expertise in FPGA architecture, RTL design, hardware validation, and board-level product development, including hands-on experience with PCBA design and system integration.
Standard Cell Design Lead Substrate IncStandard Cell Design LeadSan Francisco, CA$150,000–$275,000 / yearThis role requires deep expertise in digital cell design, layout, and timing characterization combined with strong understanding of library requirements for digital design flows. At the intersection of advanced manufacturing and cutting-edge physics, we are developing technologies that will reshape the semiconductor industry and strengthen Americas technological leadership.
Senior Asic Design Engineer Cornelis NetworksSenior Asic Design EngineerSan Jose, CARemoteCornelis Networks is seeking talented Senior ASIC Design Engineers with deep expertise in one or more of the critical areas needed to develop world-class SoCs for deployment in high-performance computing, advanced data analytics, and AI interconnect solutions. Ideal candidates will have relevant experience in the networking domain, with proven expertise in 50G, 100G, and 400G Ethernet protocols-including TCP/IP, RDMA/RoCE, and IPSec-and their application in high-speed data processing and networking environments.
Digital/RTL IC Design Engineer Omni Design Technologies IncDigital/RTL IC Design EngineerMilpitas, CAJob responsibilities include RTL design, verification, behavioral modelling, support and assist with synthesis, timing closure and P&R flow for the digital controller for high performance data converters in cutting edge technologies. We strongly believe that the pace of the ongoing hardware revolution will be greatly accelerated by Omni Design's IP cores and the rapidly emerging semiconductor embedded design business ecosystem.
Principal/Senior Staff/Staff GPGPU Design Engineer SQL PagerPrincipal/Senior Staff/Staff GPGPU Design EngineerSan Francisco, CaliforniaNice to have Prior experience of a GPU functional blocks, including Caches• Knowledge in various DNN networks and their core ASIC implementations• Knowledge of Graphics/Compute APIs, such as CUDA/OpenCL• Knowledge of OS, software/hardware interface• Finite Precision Analysis of multi-layer compute processing pipeline. In-depth Knowledge of one of the parallel processing hardware architectures Neural Network Computation Flow on GPU/NPU Array/Vector/Systolic Processors SIMD/SIMT Processing Pipelines Base Jump manycore GPU cache hierarch and Latency-hiding with NoC Inter-connect bus fabric.
Senior Digital Design Engineer SQL PagerSenior Digital Design EngineerSan Jose, CaliforniaHands on experience of ASIC design flow including RTL design, verification, Lint, CDC, LEC, logic synthesis, DFT, timing analysis, floor-planning, GLS, ECO, bring-up & lab debug. Preferred Qualifications: Hands on design experience in PCIe logical / link / transaction layers.
Digital Design Engineer SQL PagerDigital Design EngineerSan Jose, CaliforniaHands on experience of ASIC design flow including RTL design, verification, Lint, CDC, LEC, logic synthesis, DFT, timing analysis, floor-planning, GLS, ECO, bring-up & lab debug. Preferred Qualifications: Hands on design experience in PCIe logical / link / transaction layers.
Digital Design Engineer HPDigital Design EngineerSan Francisco, California$107,400–$155,700 / yearAs a member of the team, you'll have the opportunity to contribute across the digital design process, develop your craft alongside experienced designers and engineers, and help create new interfaces, interactions, and experiences that shape our product roadmap. We’re especially interested in candidates who have experience or demonstrated interest in any of the following areas: High-fidelity prototyping using code or tools such as Origami Studio, SwiftUI, WebGL, JavaScript, or CSS.
Digital Design Engineer Intern Analog Devices IncDigital Design Engineer InternSan Jose, CA$19–$35 / hourADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.
Principal Design Verification Engineer Silicon Engineering Space Exploration Technologies CorpPrincipal Design Verification Engineer Silicon EngineeringSunnyvale, CA$210,000–$310,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Associate Digital Design Engineer Analog DevicesAssociate Digital Design EngineerSan Jose, CaliforniaADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.