Senior Asic Design Engineer - Clocks IP NvidiaSenior Asic Design Engineer - Clocks IPSanta Clara, CAImprove Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
Senior Software Engineer, Hardware Tools And Methodology Development NvidiaSenior Software Engineer, Hardware Tools And Methodology DevelopmentSanta Clara, CAThe base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits. Architect automated workflows for supporting deliverables to multiple cross functional teams.
Senior DFT Power Methodology Engineer NvidiaSenior DFT Power Methodology EngineerSanta Clara, CADesign-for-X Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions in AI for Chip Design and AI for Predictions in various use cases in manufacturing testing on some of the industry's most complex semiconductor chips. You will work with multi-functional teams including Product Development & Power Architecture, implementing brand-new methodologies on hard-to-solve problems for improving our outgoing quality of chips.
Principal Photonics IC Design Engineer NvidiaPrincipal Photonics IC Design EngineerSanta Clara, CAWe are looking for a Principal Photonics IC Design Engineer to serve as the technical lead owning our photonics integrated circuit (PIC) product - from architecture definition through production tapeout and silicon validation. What We Need to See: PhD in Electrical Engineering, Physics, Applied Physics, or a closely related field with emphasis on integrated photonics, silicon photonics, or photonic device physics (or equivalent experience).
DFT Engineer - New College Grad NvidiaDFT Engineer - New College GradSanta Clara, CAOur Design-for-Test Engineering team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. Excellent analytical skills in verification and validation of test patterns and logic on sophisticated and multi-million gate designs using vendor tools.
Systems Quality And Reliability Lead - LPU NvidiaSystems Quality And Reliability Lead - LPUSanta Clara, CAManage operational perf of FA at CMs, ensuring partner achieve key perf indicators including FA cycle times, fault duplication rates and fault isolation rates. Oversee hardware quality performance, monitoring field quality data and associated metrics including RMA rates, MTBF, and Reliability Ratio.
Systems Quality And Reliability Engineer - LPU NvidiaSystems Quality And Reliability Engineer - LPUSanta Clara, CAManage operational perf of FA at CMs, ensuring partner achieve key perf indicators including FA cycle times, fault duplication rates and fault isolation rates. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.
NewSenior C++ Software Engineer - Chip Design Tools NvidiaSenior C++ Software Engineer - Chip Design ToolsSanta Clara, CAThe base salary range is 152,000 USD - 241,500 USD for Level 3, and 184,000 USD - 287,500 USD for Level 4. You will also be eligible for equity and benefits. Our team is responsible for development and support of infrastructure tools used by design engineers for build and verification of architectural, rtl, and gate level designs.
NewSenior Physical Design Engineer NvidiaSenior Physical Design EngineerSanta Clara, CAAlready a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR-RC/ICV),Cadence (Innovus, Tempus, SeaHawk ) and Mentor Graphics. As a member of a team, we will all participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure.
NewSignal And Power Integrity Engineer - Hardware NvidiaSignal And Power Integrity Engineer - HardwareSanta Clara, CABackground with use of VNA, TDR, DSO, ParBERT and use of tools/applications like ADS, Ansys Designer, JMP, Matlab, Cadence Allegro will be a plus. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.
NewSenior Asic Physical Design Engineer, Netlisting NvidiaSenior Asic Physical Design Engineer, NetlistingSanta Clara, CAWhat you'll be doing: You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.
NewSenior Analog And Mixed Signal Engineer NvidiaSenior Analog And Mixed Signal EngineerSanta Clara, CAWhat you'll be doing: You will work as part of a team to design and implement high speed interfaces and complex mixed-signal circuits using state-of-the-art sub-micron CMOS technologies and various EDA tools: High speed analog and hybrid Phase Locked loops and associated subblocks including VCO, charge-pump, dividers, state machines, LDO, bandgap, TDC, interpolator circuits, high speed buffers etc. Your other responsibilities will include architecture studies, circuit designs & simulations, floor-planning, instructing mask designers, reliability verifications and silicon bring-up.
NewSignal And Power Integrity Engineer NvidiaSignal And Power Integrity EngineerSanta Clara, CAFamiliarity with use of VNA, TDR, DSO, ParBERT and use of tools/applications like ADS, Ansys Designer, JMP, Matlab, Cadence Allegro. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.
NewSenior SRAM Engineer NVIDIA CorpSenior SRAM EngineerSanta Clara, CABe it high speed, low power, multiport, we engage closely with processor architecture teams to build custom solutions across the entire NVIDIA silicon portfolio. Improve/develop flows and methodologies to streamline design automation, data collection, and analysis to ensure working silicon.
Senior ML Engineer, Metropolis NvidiaSenior ML Engineer, MetropolisSanta Clara, CAIf you are driven to push generative AI, simulation, and large-scale model development forward and want your work to impact real-world systems, we invite you to apply. NVIDIA's Metropolis team advances physical AI by building intelligent video analytics and perception solutions for smart cities, industrial automation, and autonomous systems at scale.
Director, Adas User Experience Product - Autonomous Vehicles NvidiaDirector, Adas User Experience Product - Autonomous VehiclesSanta Clara, CA15+ overall years' experience in product management, 8+ years of experience managing a team and 7+ years of overall proven experience preferably within the automotive industry or related fields. Proactive approach to product development, including hands-on driving, testing, and shaping the product experience and eagerness to embrace challenges and immerse oneself directly in product details.
Sidecar Careers - Junior Business Analyst Engineer SidecarSidecar Careers - Junior Business Analyst EngineerSan Francisco, CAOur office is located in downtown San Francisco and is full of smart, hard-working people collaborating to bring ride-sharing to everyone… and having a great time along the way! Comfortable communicating cross-functionally and across management levels in formal and informal settings.
Senior SOC Design Engineer NvidiaSenior SOC Design EngineerSanta Clara, CAAs a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software, DFT, and more. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.
Commercial Roofing Estimator Tecta & SchwickertsCommercial Roofing EstimatorMuskogee, OKFull timeThis role analyzes project plans and specifications, performs material take-offs, assesses labor and equipment needs, and supports the sales and operations teams to ensure profitable and timely project execution. Job Requirements: High school diploma or equivalent (associate’s or bachelor’s degree in construction management, engineering, or related field preferred).
Senior Asic Timing Engineer, DFT NvidiaSenior Asic Timing Engineer, DFTSanta Clara, CAWhat you'll be doing: Drive timing analysis and closure for DFT logic on all Nvidia chips (GPUs/CPUs/DPUs/LPUs/SoCs) at all hierarchical levels (block/cluster/full-chip). Work with PD, DFX, Clocks and other teams to come up with timing closure strategy, develop timing constraints for custom DFT designs, drive timing and power convergence, and implement ECOs.