The role spans key core areas such as Frontend, Midcore, Load-Store Unit, Hardware Prefetch, and Vector Unit / vector microarchitectural interactions, and is aimed at an engineer who can independently own complex verification problems, define verification strategy early, identify microarchitectural risk, and raise verification quality across the broader CPU DV effort. Define effective verification approaches for challenging behaviors such as branch prediction, instruction fetch, issue and dispatch behavior, pipeline interactions, hazard handling, load/store ordering, memory consistency, exception and recovery behavior, hardware prefetch correctness, and vector execution correctness.