Third, provide strategic technical and organizational leadership by connecting Design, DFT, Product Engineering, Test Engineering, Failure Analysis, Yield Engineering, Automation, and AI teams around difficult cross-cutting problems and executable technical roadmaps. 12+ years of semiconductor engineering experience, including significant work in ATPG or memory diagnostics, DFT, silicon debug, product or test engineering, yield analysis, Failure Analysis, Design for Debug, Design for Yield, or post-silicon engineering.