Software Engineer - Cloud Guidewire Software IncSoftware Engineer - CloudSan Mateo, CA$86,000–$130,000 / yearDevelop Multi-Tenant Cloud Platform that caters to running all Guidewire applications and services (Refer: https://medium.com/guidewire-engineering-blog/guidewire-cloud-why-hybrid-tenancy-is-the-right-choice-56a0ff176032 , https://medium.com/guidewire-engineering-blog/guidewire-cloud-why-hybrid-tenancy-is-the-right-choice-part-2-of-2-ba22c9888bb8 . At Guidewire, we foster a culture of curiosity, innovation, and responsible use of AI-empowering our teams to continuously leverage emerging technologies and data-driven insights to enhance productivity and outcomes.
Senior Power Engineer Zp Group LlcSenior Power EngineerSaratoga, CA$210,000–$260,000 / yearKeywords: Power Engineer, Senior Power Engineer, Power Electronics, Power Delivery Network, PDN, DC‑DC Conversion, Multi‑Phase Regulators, IR‑Drop, Power Integrity, High‑Power ASIC, BGA Packaging, AI Hardware, Data Center Power, OCP Power, SPICE Simulation, AI Systems, High‑Performance Computing, PCB Power, Power Module Design, Power Architecture Engineer, Semiconductor Power Delivery, Low‑Voltage High‑Current, Power Systems Engineer, Power Supply Design, Electrical Engineer, Hardware Engineering, Mixed‑Signal Power. Piper Companies is looking for a Senior Power Engineer to join a cutting edge startup specializing in next‑generation AI, high‑performance compute, and advanced networking hardware located near San Jose, CA to lead the design and development of high‑efficiency power delivery solutions supporting cutting‑edge semiconductor and AI platforms.
Senior ASIC Design Engineer Zp Group LlcSenior ASIC Design EngineerSaratoga, CA$250,000–$290,000 / yearKeywords: ASIC, ASIC Architect, Networking ASIC, AI Networking, Design, Microarchitecture, Performance Modeling, PCIe, SerDes, Ethernet, TCP/IP, RoCE, High-Speed Datapath, Silicon Validation, System-on-Chip, SoC Architecture, Hardware Design, IP Integration, Physical Design, Firmware Interface, Chip Architect, DPU, CPU, SOC. Qualifications for Senior ASIC Design Engineer: 10+ years of experience as an Chip Architect, preferably in networking or high-performance computing (Routers, Switches, GPU, CPU, Data Center, etc).
Senior Software Engineer, Front End, Pomelli Google LLCSenior Software Engineer, Front End, PomelliMountain View, CAWe"re looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. Experience applying Machine Learning and Artificial Intelligence (specifically language and multi-modal technologies) to create intelligent agents and automated tools for users.
Product Design Engineer, Google Beam Google LLCProduct Design Engineer, Google BeamMountain View, CA$159,000–$231,000 / yearCareers Skip navigation links home home Home Homework_outlinework_outline Jobs Jobs noogler_hat noogler_hat Students Students google google How we work How we work handyman handyman How we hire How we hire person_outline person_outline Your career Your career help_outline Help link feedback Send feedback more_vert Help Send Feedback Sign in. Careers Careers home Home Homework_outline Jobs expand_more noogler_hat Students expand_more google How we work expand_more handyman How we hire expand_more person_outline Your career expand_more.
Senior Staff Software Engineer, ML Infrastructure, Agents Infrastructure Google LLCSenior Staff Software Engineer, ML Infrastructure, Agents InfrastructureSunnyvale, CAWere looking for engineers who bring fresh ideas from all areas including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. Careers Skip navigation links home Home work_outline Jobs noogler_hat Students google How we work handyman How we hire person_outline Your career help_outline Help link feedback Send feedback more_vert Help Send Feedback Sign in.
Member of Technical Staff, Software Engineer InceptionMember of Technical Staff, Software EngineerSan MateoInception was co-founded by Stanford professor Stefano Ermon , who co-invented such breakthrough AI technologies as diffusion models, flash attention, and DPO, UCLA professor Aditya Grover , who co-invented node2vec, decision transformers, and d1 reasoning, and Cornell professor and Afresh co-founder Volodymyr Kuleshov , who co-invented MDLM and Block Diffusion. Based in Palo Alto, CA, we are backed by top-tier venture capitalists, including Menlo Ventures, Mayfield, M12 (Microsoft’s venture fund), Snowflake Ventures, Databricks, and Innovation Endeavors, and by tech luminaries such as Andrew Ng, Andrej Karpathy, and Eric Schmidt.
Test Engineer-Ai/Llm OPPO US Research CenterTest Engineer-Ai/LlmPalo Alto, CAIn this critical role, you will evaluate the performance, reliability, and safety of Large Language Models (LLMs) in real-world product scenarios and test end-to-end generative AI solutions. You will help implement test strategies, execute evaluation workflows, and assist in model performance validation across diverse generative AI use cases.
Test Engineer-AI/LLM OPPO US Research CenterTest Engineer-AI/LLMPalo Alto, CAIn this critical role, you will evaluate the performance, reliability, and safety of Large Language Models (LLMs) in real-world product scenarios and test end-to-end generative AI solutions. You will help implement test strategies, execute evaluation workflows, and assist in model performance validation across diverse generative AI use cases.
ASIC Implementation Engineer - Static Verification Meta Platforms IncASIC Implementation Engineer - Static VerificationSunnyvale, CADegree must be completed prior to joining Meta 2+ years of experience in static verification tools Experience with Lint, Clock Domain & Reset Domain crossing Experience with SOC CDC signoff Knowledge of SOC Integration (Clocking, Reset, PLL, etc) Knowledge of front-end ASIC flows Experience with RTL design using SystemVerilog or other HDL Experience with communicating across functional internal teams and vendors Experience with SOC Design Integration and Front-End Implementation Experience with Netlist-CDC Analysis and improving MTBF Knowledge of Timing/physical libraries, SRAM Memories Scripting and programming experience using Perl/Python, TCL, and Make Experience with developing structural rule based checks for RTL & Netlist Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent toolsMeta builds technologies that help people connect, find communities, and grow businesses. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC,) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks.
Associate Product Engineer (College Grad 2027) Find Solace IncAssociate Product Engineer (College Grad 2027)Redwood City, CAYoull join a spectacularly talented team who will push you to grow, but youll also be expected to think independently, ask the right questions, and own your work from design through deployment. Solace cuts through the red tape of healthcare by pairing patients with expert advocates and giving them the tools to make better decisions-and get better outcomes.
Software Engineer II Bear RoboticsSoftware Engineer IIRedwood City, CA$176,000–$215,000 / yearCollaborate with architects and cross-functional teams to contribute to the design of complex software systems, focusing on scalability, performance, and maintainability. We have developed robotic solutions that autonomously navigate indoor environments for a variety of consumer solutions, like restaurants, senior living facilities, hotels & casinos just to name a few.
Senior Staff ML Software Engineer, AI Generated Content Quality, Search Discover Feed Google LLCSenior Staff ML Software Engineer, AI Generated Content Quality, Search Discover FeedMountain View, CAWere looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. 7 years of experience leading technical project strategy, ML design, and working with industry-scale ML infrastructure (e.g., model deployment, model evaluation, data processing, debugging, fine tuning).
NewSoftware Engineer III, Diags Infrastructure Google LLCSoftware Engineer III, Diags InfrastructureSunnyvale, CAWere looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. Our teams mission is to engineer diagnostic infrastructure, qualification frameworks, and dynamic distribution systems to minimize Mean Time To Repair (MTTR) and maximize useful hardware coverage.
Staff Software Engineer, AI and Infrastructure Google LLCStaff Software Engineer, AI and InfrastructureSunnyvale, CAThe Borglet Infrastructure group in Borglet is a team of 30 SWEs (distributed between Sunnyvale and Warsaw) developing core pieces of Borglet (Software Architecture, Runtime, Machine Management, Storage) to deliver the container infrastructure that is scalable, extensible, efficient and secure. Collaborate with partner teams as well as users across Google e.g., Borg team, ML teams, HW platform teams, SRE teams, Googles internal and Cloud users.
ASIC Design Verification Engineer, TPU Compute Google LLCASIC Design Verification Engineer, TPU ComputeSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Were the driving force behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Staff Software Engineer, Network Infrastructure Capacity Delivery Google LLCStaff Software Engineer, Network Infrastructure Capacity DeliverySunnyvale, CAWere looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
NewASIC Implementation Engineer, Static Verification Meta Platforms IncASIC Implementation Engineer, Static VerificationSunnyvale, CAInteract with Physical Design Engineers and provide them with timing/congestion feedbackBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience Currently has a Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience 6+ years of experience in static verification tools Experience with Lint, Clock Domain and Reset Domain crossing Experience with SOC CDC signoff Knowledge of SOC integration (clocking, reset, PLL, etc.) Knowledge of front-end ASIC flows Experience with RTL design using SystemVerilog or other HDL Experience with communicating across functional internal teams and vendors Experience with Netlist-CDC Analysis and improving MTBF Experience with SOC Design Integration and Front-End Implementation Scripting and programming experience using Perl/Python, TCL, and Make Experience with developing structural rule based checks for RTL & Netlist Experience with Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools Knowledge of Timing/physical libraries, SRAM MemoriesMeta builds technologies that help people connect, find communities, and grow businesses. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC,) Work closely with the Design Engineers, DV Engineers, and Emulation Engineers in supporting them with the handoff tasks.
Senior ASIC Cloud Design Verification Engineer Google LLCSenior ASIC Cloud Design Verification EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Were the driving team behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Chip Package Signal and Power Integrity Engineer Google LLCChip Package Signal and Power Integrity EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Were the driving force behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.