Lead Mechanical Engineer, Hardware Reliability Starlink Space Exploration Technologies CorpLead Mechanical Engineer, Hardware Reliability StarlinkBastrop, TXLeadership: Lead and mentor a team of engineers and specialists focused on hardware reliability and field performance for the Starlink User Terminal Kit, including user terminals, Wi-Fi routers, power supplies, and cables. Define and monitor ongoing reliability testing and monitoring strategies to assess manufacturing process health and identify long-term reliability risks driven by process, material, and component variability.
Senior ASIC Timing Engineer NVIDIA CorpSenior ASIC Timing EngineerAustin, TXCollaborate with Cross-Functional Teams: Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create timing constraints, and drive timing and power convergence as well as implement ECOs. What you'll be doing: Drive Timing Analysis and Closure: Lead the timing analysis and closure processes for NVIDIA's GPUs, CPUs, LPUs, and SoCs at block level, cluster level, and full chip level.
Senior ASIC Design Engineer – Clocks IP NVIDIASenior ASIC Design Engineer – Clocks IPAustin, CaliforniaImprove Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
Senior Asic Timing Engineer NvidiaSenior Asic Timing EngineerAustin, TXCollaborate with Cross-Functional Teams: Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create timing constraints, and drive timing and power convergence as well as implement ECOs. What you'll be doing: Drive Timing Analysis and Closure: Lead the timing analysis and closure processes for NVIDIA's GPUs, CPUs, LPUs, and SoCs at block level, cluster level, and full chip level.
Senior Asic Design Engineer - Clocks IP NvidiaSenior Asic Design Engineer - Clocks IPAustin, TXImprove Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
Senior Asic Physical Design Engineer, Netlisting NvidiaSenior Asic Physical Design Engineer, NetlistingAustin, TXWhat you'll be doing: You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.
NewSenior ASIC Physical Design Engineer, Netlisting NVIDIASenior ASIC Physical Design Engineer, NetlistingAustin, CaliforniaYou will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits .
Test Engineer TPI Global (formerly Tech Providers, Inc.)Test EngineerAustin, TXEducation: Bachelor's or Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field. •Experience with PCIe, CXL, DDR Memory Validation, RAS, Power Management, Virtualization, or Platform Security features.
Validation Engineer LancesoftValidation EngineerAUSTIN, TX$50Collaborate with Design, Software, Tools and other teams to drive the definition of testing and debug methodologies to provide the best possible coverage and customer experience for the *** internal address and data hub subsystem. As an IP Systems Engineer, you will drive the planning, post-silicon execution, silicon bring-up and debug of *** processor and graphics based systems while working closely with internal teams to meet product development milestones.
Sr. Embedded Systems Engineer ThermonSr. Embedded Systems EngineerAustin, TXFull timeWho We WantWe're looking for a Senior Embedded Systems Engineer to join our R&D Controls and Accessories Team and help build the next generation of industrial control hardware and IIoT-connected devices. Familiarity with industrial communication protocols (Modbus, CAN Bus, RS-485, BACNet).· Experience reading and reviewing schematics and PCB layouts (Altium Designer or equivalent).·
NewSoftware Development Test Engineer (Starlink) SpaceXSoftware Development Test Engineer (Starlink)Bastrop, TXDesign, build, and maintain highly reliable hardware-in-the-loop (HIL/HITL) testbeds—including surrounding infrastructure, tooling, and support equipment—for the Starlink software continuous integration system. To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
NewLead Electronics Engineer, Gateways (Starlink) Space Exploration TechnologiesLead Electronics Engineer, Gateways (Starlink)Bastrop, TX6+ years of experience designing and implementing mixed-signal circuit boards from concept through production using processors, FPGAs, Ethernet, multi-GHz Serdes, DRAM interfaces (DDR4), I2C, SPI, operational amplifiers, analog to digital and digital to analog converters, and power supply components. As the Lead Electronics Engineer on the Starlink team, you will be responsible for the design, performance, and reliability of next-generation gateways - ultimately ensuring that our ground station antenna hardware can withstand the harshest environmental conditions while maintaining reliable communication with millions of users on a global scale.
MEP/Construction Engineer SpaceXMEP/Construction EngineerBastrop, TXTo conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. As a member of the Construction Projects Team, you will work with engineers across multiple disciplines to design, build, and activate infrastructure that will enable SpaceX to achieve its long-term mission.
Sr. Hardware Engineer, Gateways & Customer Hardware (Starlink) SpaceXSr. Hardware Engineer, Gateways & Customer Hardware (Starlink)Bastrop, TX8+ years of experience designing and implementing mixed-signal circuit boards from concept through production using processors, FPGAs, Ethernet, multi-GHz Serdes, DRAM interfaces (DDR4), I2C, SPI, operational amplifiers, analog to digital and digital to analog converters, and power supply components. Our customers currently include teachers in the most remote parts of the Amazon, researchers in Antarctica, digital nomads who travel via RV, emergency responders, commercial airlines, cruise lines, and residential users who live in more rural or developing areas.
Facilities Engineer, Mechanical (Starlink) Space Exploration TechnologiesFacilities Engineer, Mechanical (Starlink)Bastrop, TXITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. As a member of the Construction Projects Team, you will work with engineers across multiple disciplines to design, build, and activate infrastructure that will enable SpaceX to achieve its long-term mission.
Mechanical Engineer, Infrastructure Space Exploration TechnologiesMechanical Engineer, InfrastructureBastrop, TXITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. As a member of the Construction Projects Team, you will work with engineers across multiple disciplines to design, build, and activate infrastructure that will enable SpaceX to achieve its long-term mission.
Wi-Fi Engineer, Hardware Reliability (Starlink) SpaceXWi-Fi Engineer, Hardware Reliability (Starlink)Bastrop, TXWe provide reliable and fast internet to millions of users worldwide, including populations with little or no connectivity, rural communities, aircraft, watercraft, and places where existing services are unreliable, too expensive, or disconnected by natural disasters. To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
Lead Electronics Engineer, Gateways (Starlink) SpaceXLead Electronics Engineer, Gateways (Starlink)Bastrop, TX6+ years of experience designing and implementing mixed-signal circuit boards from concept through production using processors, FPGAs, Ethernet, multi-GHz Serdes, DRAM interfaces (DDR4), I2C, SPI, operational amplifiers, analog to digital and digital to analog converters, and power supply components. As the Lead Electronics Engineer on the Starlink team, you will be responsible for the design, performance, and reliability of next-generation gateways - ultimately ensuring that our ground station antenna hardware can withstand the harshest environmental conditions while maintaining reliable communication with millions of users on a global scale.
Mechanical Engineer, Infrastructure SpaceXMechanical Engineer, InfrastructureBastrop, TXTo conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. As a member of the Construction Projects Team, you will work with engineers across multiple disciplines to design, build, and activate infrastructure that will enable SpaceX to achieve its long-term mission.
Sr. Hardware Engineer, Gateways & Customer Hardware (Starlink) Space Exploration TechnologiesSr. Hardware Engineer, Gateways & Customer Hardware (Starlink)Bastrop, TX8+ years of experience designing and implementing mixed-signal circuit boards from concept through production using processors, FPGAs, Ethernet, multi-GHz Serdes, DRAM interfaces (DDR4), I2C, SPI, operational amplifiers, analog to digital and digital to analog converters, and power supply components. Our customers currently include teachers in the most remote parts of the Amazon, researchers in Antarctica, digital nomads who travel via RV, emergency responders, commercial airlines, cruise lines, and residential users who live in more rural or developing areas.