Advanced Packaging Reliability Engineer OpenAIAdvanced Packaging Reliability EngineerSan Francisco, CaliforniaFor unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In-depth knowledge of advanced packaging architectures, including 2.5D and 3.5D integration, interposers, embedded bridges, chiplets, large package substrates, HBM integration, redistribution layers, and package-level power delivery.
Aerospace Harnessing Engineer (Launch Vehicle Avionics) The Valentino GroupAerospace Harnessing Engineer (Launch Vehicle Avionics)Alameda, CaliforniaAs a Harnessing Engineer, you'll own the design and execution of flight and test harnesses that connect avionics, sensors, power systems, and vehicle subsystems—ensuring reliability in extreme environments. Youll work closely with mechanical, thermal, electrical, integration, and manufacturing teams to deliver harness systems that are safe, lightweight, manufacturable, and flight-ready.
Senior Electrical Engineer- Space Vector Atomic Inc.Senior Electrical Engineer- SpacePleasanton, CAThe Role: We're looking for a Senior Electrical Engineer to join a multidisciplinary team of physicists and electrical, mechanical, software, and optical engineers designing next-generation quantum sensors for Low Earth Orbit (LEO) missions. The company is accelerating its technology roadmap and intends to deliver the world's most powerful quantum computers with 2 million qubits by 2030 to accelerate innovation in drug discovery, materials science, financial modeling, logistics, cybersecurity, and defense.
NewSenior Software Engineer - Optical Transceiver Koch IncSenior Software Engineer - Optical TransceiverFremont, CA$140,000–$190,000 / yearSenior Software Engineer - Optical Transceiver - Fremont, California, United States - 188444 - Koch. Join our Talent Community.
Senior Circuit Design Engineer NvidiaSenior Circuit Design EngineerSanta Clara, CAMore recently, GPU deep learning ignited modern AI - the next era of computing - with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.
Senior Design Engineer, Coherent High Speed Interconnect NvidiaSenior Design Engineer, Coherent High Speed InterconnectSanta Clara, CAThe NVLINK-C2C enables the creation of a new class of integrated products with NVIDIA partners, built via chiplets, allowing NVIDIA GPUs, DPUs, and CPUs to be coherently interconnected with custom silicon. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.
Package Design Engineer Broadcom CorporationPackage Design EngineerSan Jose, CARESPONSIBILITIES: Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts. Job Description: Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs.
Product Design Engineer xponentiateProduct Design EngineerSan Francisco, CAThe position oversees command palette user experience, screen flows, accessibility features, and delivers frequent product previews. The role is hybrid with onsite collaboration in San Francisco, focused on fast-paced, iterative shipping of design improvements.
Lead Asic Design Engineer Broadcom CorporationLead Asic Design EngineerSan Jose, CA$143,800–$230,000 / yearRTL Design: Author, optimize, and maintain high-quality, synthesizable SystemVerilog/Verilog RTL for complex digital blocks, control logic, clocking structures, and register files (CSRs). Front-End Flows: Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis (STA via PrimeTime/Tempus), and run static quality checks (Lint, SpyGlass, JasperGold CDC).
Physical Design Engineer Broadcom CorporationPhysical Design EngineerSan Jose, CAThis position involves working with the latest technology to continue driving next generation AI/ML ecosystems through our PCIe Switch Products - and managing mega datacenters, while leading world class performance, through our Enterprise Storage Products. As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.
Physical IC Design Engineer Broadcom CorporationPhysical IC Design EngineerSan Jose, CA$143,800–$230,000 / yearThis position involves working with the latest technology to continue driving next generation Artificial Intelligence and Machine Learning ecosystems through our PCIe Switch Products - and managing mega datacenters, while leading world class performance, through our Enterprise Storage Products. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Principal Photonics IC Design Engineer NvidiaPrincipal Photonics IC Design EngineerSanta Clara, CAWe are looking for a Principal Photonics IC Design Engineer to serve as the technical lead owning our photonics integrated circuit (PIC) product - from architecture definition through production tapeout and silicon validation. What We Need to See: PhD in Electrical Engineering, Physics, Applied Physics, or a closely related field with emphasis on integrated photonics, silicon photonics, or photonic device physics (or equivalent experience).
Design Engineer WorkOSDesign EngineerSan Francisco, CaliforniaRemoteAs AI reshapes software, WorkOS is at the frontier of Human and Agent Authentication, Identity, and Access Control helping companies answer a new critical question: who are your agents, and what are they allowed to do? You’ll help bring ambitious ideas to life by prototyping directly in code, validating with customers, and shipping production experiences with a high bar for craft.
Circuit Design Engineer - New College Grad 2026 NvidiaCircuit Design Engineer - New College Grad 2026Santa Clara, CAMore recently, GPU deep learning ignited modern AI - the next era of computing - with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA's invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing.
Asic Design Engineer - New College Grad 2026 NvidiaAsic Design Engineer - New College Grad 2026Santa Clara, CAThis position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What you'll be doing: As a key member of the GPU Design team, you will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications.
Senior Photonic Layout Design Engineer NvidiaSenior Photonic Layout Design EngineerSanta Clara, CAAutomation & AI-Assisted Workflows: Develop and implement AI-assisted design methods, layout automation scripts, and custom Pcells to improve productivity, reduce development cycle times, and customize DRC/LVS checking flows. What You'll Be Doing: As a Senior Photonics Layout Engineer, you will take ownership of the physical design and verification of cutting-edge photonic integrated circuits (PICs), guiding designs from initial proof-of-concept phases to high-volume manufacturing readiness.
Senior Asic Design Engineer - DFX NvidiaSenior Asic Design Engineer - DFXSanta Clara, CADesign-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. What You'll Be Doing: As a key member of our DFX Methodology Team, you will play a critical role in shaping the architecture, design, implementation, and verification of DFT IPs for our next-generation SoC products.
Design Engineer III eTeam Inc.Design Engineer IIISunnyvale, CAPerform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams. About the role: Design Verification engineer for wearables silicon accelerator IPs testbench development, coverage-driven verification, RTL debug, and power/performance measurement.
NewSenior Physical Design Engineer NvidiaSenior Physical Design EngineerSanta Clara, CAAlready a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR-RC/ICV),Cadence (Innovus, Tempus, SeaHawk ) and Mentor Graphics. As a member of a team, we will all participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure.
NewSenior PA Design Engineer QorvoSenior PA Design EngineerSan Jose, CA$115,600–$150,500 / yearQorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. As a Staff Power Amplifier (PA) Design Engineer, you will be involved in the design and development of high-efficiency and high-linearity Cellular Power Amplifiers (PAs) and RF Front-End Modules (FEMs) for next-generation 5G NR and 6G smartphones.