Experience designing, integrating, and verifying DDR memory interfaces (e.g., DDR3/DDR4/DDR5) and fabric-based controllers (such as AXI or custom interconnects) in FPGA designs, including expertise in IP configuration, timing closure, signal integrity, and high-throughput data movement. Knowledgeable in managing design constraints (timing, power, I/O) and performing static timing analysis to achieve critical performance targets using Vivado IDE; Proficient in development, verification, and debugging of MOSA interfaces/buses (Ethernet, PCIe, AXI4, UART, and SDLC).