Sr. Staff/Staff Engineer, Digital Design InnoPhase IoTSr. Staff/Staff Engineer, Digital DesignSan Jose, CAIf you are keen to work with a bunch of brilliant people with various backgrounds, if you share the same value of working smart and celebrating successes, if you have enthusiasm for big technology in a small company, if your goals are to learn and experience different aspects of work--not just singing the same song every day, you'll find your playground at Innophase IoT. In addition to delivering high quality digital solutions, the team supports other disciplines with work product such as Verilog stimulus files, test benches for device bring up/characterization, test vectors for product manufacturing.
Senior Design Engineer (MOSFET / IGBT) Alpha & Omega SemiconductorSenior Design Engineer (MOSFET / IGBT)Sunnyvale, CAFull timeAt Alpha and Omega Semiconductor (AOS), we design, develop and globally supply a broad range of power semiconductors, including a wide portfolio of Power MOSFET, IGBT, IPM, TVS, GaN/SiC, Power IC and Digital Power products. Primary job functions include:Power device structure and process simulation with TCAD tools including Tsuprem4, Medici, and SentaurusDevice characterization with LCR meter, curve tracer, FET test, etc.
AutoCAD Design/Drafter Auriga CorporationAutoCAD Design/DrafterMilpitas, CaliforniaAURIGA JOB POSTING (Auriga Website: www.aurigacorp.com ) Auriga Corporation was established in 1990, to provide high-quality design, engineering and project management services for Electric Power, Telecommunication and Information Technology systems. Auriga Corporation continues to provide Consulting Services to the Rail and Transit Systems, Municipal Utilities, United States Federal Government, The State of California, International Governments and International Public and Private Sector Organizations.
FPGA Design Engineer - Avionics E-SpaceFPGA Design Engineer - AvionicsSaratoga, CAOur team members have a strong sense of dedication and responsibility; this includes a strong commitment to our mission to create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.
RFIC Design Engineer , Amazon Leo Amazon.com IncRFIC Design Engineer , Amazon LeoSunnyvale, CAExplore architectures for mm-wave and RF circuits like VCOs, mixers, phase shifters, LNAs, PAs, LO distribution, frequency multipliers and dividers, and envelope/power detectors, and make detailed presentations on power/area/performance trade-offs. Collaborate with communications systems, digital design, and chip implementation teams to specify and implement transceivers and RFIC front-end models which will delight future Kuiper customers.
Senior CAD Engineer, RTL Design, Silicon, Google Cloud Google LLCSenior CAD Engineer, RTL Design, Silicon, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Were the driving force behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
RTL Design Engineer, Machine Learning Accelerators Google LLCRTL Design Engineer, Machine Learning AcceleratorsSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing with key teams working on the development of our TPUs Vertex AI for Google Cloud Google Global Networking Data Center operations systems research and much more. Careers Skip navigation links home Home Homework_outlinework_outline Jobs noogler_hat Students google How we work handyman How we hire person_outline Your career help_outline Help link feedback Send feedback more_vert Help Send Feedback Sign in.
RTL Design Engineer, Machine Learning Google LLCRTL Design Engineer, Machine LearningSunnyvale, CAFrom software to hardware, our teams are shaping the future of world-leading hyperscale computing with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research and much more. Youll contribute to the innovation behind products loved by millions worldwide and leverage your design and verification expertise to verify complex digital designs with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Senior Design Verification Engineer Google LLCSenior Design Verification EngineerMountain View, CAApplyshare linkCopy linkemailEmail a friendMinimum qualificationsBachelors degree in Electrical Engineering Computer Engineering Computer Science a related field or equivalent practical experience.8 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience with different verification techniques and methodologies including formal GLS UPF based Power simulations UVM and C based testing etc. to achieve bug-free Silicon in complex SoCs.
Senior RTL Design Engineer MythicSenior RTL Design EngineerPalo Alto, CA$120,000–$225,000 / yearWe've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets. Because today's AI workloads push the limits of performance, memory, and efficiency, our RTL engineers apply both creativity and rigor to deliver designs that meet aggressive PPA (performance, power, area) goals while ensuring correctness.
RTL Design Engineer MythicRTL Design EngineerPalo Alto, CA$120,000–$225,000 / yearWe're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. We've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets.
Sr Mgr/Dep Director ASIC Digital Design IP ENGINEERING GlobalFoundries IncSr Mgr/Dep Director ASIC Digital Design IP ENGINEERINGSanta Clara, CA$167,000–$275,000 / yearThis role provides technical and organizational leadership for a team of digital design engineers, driving architecture implementation, RTL development, integration, verification closure support, and successful silicon execution. About GlobalFoundries: GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies.
Digital Design Flow Architect NXP Semiconductors NVDigital Design Flow ArchitectSan Jose, CAHands-on agentic AI workflow development experience, including task planning, tool invocation, result interpretation, retry logic, human-in-the-loop checkpoints, and autonomous execution patterns. Scope: Proven ability to set technical direction, influence senior stakeholders, and lead cross-functional flow transformation across functional domains or technology nodes.
ASIC Engineer, Design Meta Platforms IncASIC Engineer, DesignSunnyvale, CABachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ years of experience as a Hardware Design Engineer for production silicon shipped in volume Experience in digital design Microarchitecture, RTL coding, SoC integration and micro-architecture development Demonstrated communication and collaboration skills Master's or PhD degree in Electrical Engineering, Computer Science or related areas Experience in CPU, NOC, Memory, Die-to-die and Peripheral Subsystems Experience with Synthesis, Timing Closure and Formal Verification Methodology Experienced in managing SOC-level boot flow, Silicon Debug architectures and PLL/sequencing clocks and resets within SOC architecturesMeta builds technologies that help people connect, find communities, and grow businesses. You will collaborate with world-class researchers and engineers to design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon solutions that enable the next generation of innovative devices and hardware.
Senior ASIC Design Verification Engineer, Google Cloud Google LLCSenior ASIC Design Verification Engineer, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Were the driving force behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Creative Director, Design Meta Platforms IncCreative Director, DesignBurlingame, CAYou will partner with product designers, content designers, industrial designers, motion designers, creative technologists, and engineers to ship high-quality digital retail experiences for our expanding hardware portfolio. We have developed best-in-class collaboration models with agencies and our cross-company creative network to ensure a consistent and effective creative narrative for work that reaches an audience across the globe due to the scale of our products.
NewRTL Design Engineer, TPU Compute Google LLCRTL Design Engineer, TPU ComputeSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Were the driving force behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
NewASIC Design Verification Manager, TPU Compute Google LLCASIC Design Verification Manager, TPU ComputeSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Lead the functional verification team for significant portions of TPU Compute team, setting and communicating individual and team priorities that support organizational goals, providing regular feedback and coaching, and developing advanced functional verification infrastructure such as subchip, subsystem, and fullchip level environments.
Senior ASIC Cloud Design Verification Engineer Google LLCSenior ASIC Cloud Design Verification EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Were the driving team behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
ASIC Design Verification Manager, Google Cloud Google LLCASIC Design Verification Manager, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Guide the functional verification team for portions of TPU designs, setting and communicating individual and team priorities that support organizational goals, providing regular feedback and coaching, and developing functional verification infrastructure across subchip, subsystem, and fullchip level environments.