The role requires extensive architectural expertise across SoC subsystems and uncore IPs including PCIe/CXL, NVLink/NVLink-C2C, UCIe, AXI/CHI, NoC fabrics, memory systems, coherency, boot, system initialization, protection mechanisms, reliability, availability, serviceability, power management, debug, firmware interfaces, and platform initialization. Collaborate intimately with IP teams to develop detailed build documents for PCIe/CXL, NVLink/NVLink-C2C, UCIe, AXI/CHI, NoC fabrics, memory controllers, coherency blocks, MMUs/IOMMUs, boot, reset, and associated SoC infrastructure.