Run and debug non-timing and SDF annotated gate level simulations Analyze test results and drive test coverage improvement and closure Develop, validate and timing closure of DFT timing constraints for scan, BIST, and test modes Experience with UPF (Unified Power Format), formal verification, and DRC rule checking experience Support pre-silicon DFT signoff and assist with post-silicon pattern bring-up, debug and Silicon characterization Exposure to mixed-signal or SERDES DFT, such as IOBIST or loopback testing Exposure to Chiplet-based architectures, including Die-to-Die (D2D) test methodologies (e.g., UCIe interfaces) and Known Good Die (KGD) strategies. Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, Cell- aware, path delay fault models, diagnosis, and hierarchical test flows.