Senior Architecture Energy Modeling Engineer NVIDIASenior Architecture Energy Modeling EngineerAustin, CaliforniaAs a member of the Power Modeling, Methodology and Analysis Team, you will collaborate with Architects, ASIC Design Engineers, Low Power Engineers, Performance Engineers, Software Engineers, and Physical Design teams to study and implement energy modeling techniques for NVIDIA's next generation GPUs, CPUs and Tegra SOCs. Our team is responsible for researching, developing, and deploying methodologies to help NVIDIA's products become more energy efficient; and is responsible for building energy models that integrate into architectural simulators, RTL simulation, emulation and silicon platforms.
UX Engineer IV - (E4) Applied MaterialsUX Engineer IV - (E4)Austin, TX$156,000–$214,500 / yearThis role acts as a bridge between UX Design, Product Management, and Engineering, driving alignment, improving efficiency, and elevating the overall user experience of enterprise applications that embrace cutting-edge AI-driven workflows. If you would like to contact us regarding accessibility of our website or need assistance completing the application process, please contact us via e-mail at Accommodations_Program@amat.com, or by calling our HR Direct Help Line at 877-612-7547, option 1, and following the prompts to speak to an HR Advisor.
Principal Graphics Developer Tools Engineer NVIDIAPrincipal Graphics Developer Tools EngineerAustin, CaliforniaYou will create and lead new strategic initiatives, partnering closely with NVIDIA Research, GPU Architecture, Driver, SDK, and Developer Technology teams to evaluate emerging technologies, prototype new ideas, and deliver solutions that improve how developers build, debug, profile, and optimize graphics applications. Collaborate with GPU architects, driver engineers, SDK teams, and graphics developers to understand future needs and influence product direction.
R&D Engineer Electro Optical SystemsR&D EngineerPflugerville, TexasYour responsibilities will include independently planning and reliably conducting process tests to determine parameters and optimize processes and properties of various metallic materials using the latest laser-based technologies. You will collaborate with interdisciplinary teams, manage project tasks, and translate solutions into minimum viable products while documenting and presenting results to drive process improvements.
Senior Data Engineer Arrive LogisticsSenior Data EngineerAustin, TXDesigns, develops, and evaluates AI agents and reusable skill libraries to drive developer productivity and automate team workflows - including prompt engineering, tool integration, and performance evaluation using platforms such as Snowflake Cortex AI and LangGraph. Work with internal software engineering teams to define architectures and best practices for ingesting data into the data warehouse and making aggregated data and metrics from the data warehouse available to our production applications.
Junior Site Reliability Engineer The Charles Schwab CorpJunior Site Reliability EngineerAustin, TXIn this role, you will help support cloud and login platforms by contributing to production operations, incident response, monitoring, automation, and continuous improvement efforts that strengthen availability, maintainability, and reliability for critical application workflows. You will work alongside engineers, platform teams, and business partners to investigate technical issues, improve operational processes, reduce manual work through automation, and support dashboards, alerts, and tools that create stronger operational visibility.
Software R&D Engineer, VLSI Physical Design - New College Grad 2026 NVIDIASoftware R&D Engineer, VLSI Physical Design - New College Grad 2026Austin, TexasInvent new optimization engines that fuse traditionally independent engines (e.g., co-optimization of legalization and sizing) with the objective of increasing chip frequency while minimizing power consumption across a suite of internal optimization tools. We as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.
Senior Physical Design Engineer NVIDIASenior Physical Design EngineerAustin, CaliforniaAlready a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR-RC/ICV),Cadence (Innovus, Tempus, SeaHawk ) and Mentor Graphics. As a member of a team, we will all participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure.
Senior ASIC Design Engineer - Agentic AI NVIDIASenior ASIC Design Engineer - Agentic AIAustin, CaliforniaAs a member of the GPU Design Methodology team, you will document and deliver design guidelines that will help the ASIC team implement high performance, area and power efficient RTL to achieve design targets and specifications. This position offers the opportunity to have a real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.
Senior ASIC Physical Design Engineer, Netlisting NVIDIASenior ASIC Physical Design Engineer, NetlistingAustin, CaliforniaYou will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits .
Senior ASIC Design Engineer – Clocks IP NVIDIASenior ASIC Design Engineer – Clocks IPAustin, CaliforniaImprove Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
Senior ASIC Verification Engineer NVIDIASenior ASIC Verification EngineerAustin, TexasThe base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits . For this position, you should have real passion for verification methodologies and implementation that enable high quality system-level IP design and robust verification at multiple environment levels (e.g., unit, sub-system, and SOC).
DevOps Engineer BusPatrolDevOps EngineerAustin, TexasThat includes supporting secure, spec-driven engineering workflows, strengthening CI/CD and policy gates, improving delivery reliability, and helping teams adopt repeatable AI-enabled development practices without compromising security, compliance, or production readiness. Support secure AI-enabled software delivery by helping teams operationalize spec-driven workflows, AI-assisted PR practices, automated test generation, and controlled release readiness checks.
Founding Engineer - Abacus Pear VCFounding Engineer - AbacusAustin, TexasAbacus is reinventing how accounting firms operate by building AI agents that automate the tedious, repetitive workflows that teams currently face. Over the next year, you'll help lay the groundwork for our engineering org as we scale, while staying hands-on and focused on impact.
Signal and Power Integrity Engineer NVIDIASignal and Power Integrity EngineerAustin, CaliforniaFamiliarity with use of VNA, TDR, DSO, ParBERT and use of tools/applications like ADS, Ansys Designer, JMP, Matlab, Cadence Allegro. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.
Automation Systems Engineer - (E3) Applied MaterialsAutomation Systems Engineer - (E3)Austin, TX$120,000–$165,000 / yearIf you would like to contact us regarding accessibility of our website or need assistance completing the application process, please contact us via e-mail at Accommodations_Program@amat.com, or by calling our HR Direct Help Line at 877-612-7547, option 1, and following the prompts to speak to an HR Advisor. The salary offered to a selected candidate will be based on multiple factors including location, hire grade, job-related knowledge, skills, experience, and with consideration of internal equity of our current team members.
Signal and Power Integrity Engineer - New College Grad 2026 NVIDIASignal and Power Integrity Engineer - New College Grad 2026Austin, TexasFamiliarity with use of VNA, TDR, DSO, ParBERT and use of tools/applications like ADS, Ansys Designer, JMP, Matlab, Cadence Allegro. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.
Senior Asic Design Engineer - Clocks IP NvidiaSenior Asic Design Engineer - Clocks IPAustin, TXImprove Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
Senior Asic Verification Engineer NvidiaSenior Asic Verification EngineerAustin, TXThe base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits. For this position, you should have real passion for verification methodologies and implementation that enable high quality system-level IP design and robust verification at multiple environment levels (e.g., unit, sub-system, and SOC).
Software R&D Engineer, RTL Optimization Tools NVIDIASoftware R&D Engineer, RTL Optimization ToolsAustin, CaliforniaExplore high performance algorithms for clustering, min cost tree covering (technology mapping), datapath implementation and other details of logic synthesis, especially that efficiently incorporate human insight. Experience with common EDA building blocks, such as Verific for Verilog parsing, Espresso for logic minimization, and various other components for logic rewriting, tree coverage, SAT solvers, and combinatorial optimization.