Strong preference for candidates with experience from semiconductor foundries, advanced packaging organizations (OSATs), integrated device manufacturers (IDMs), or EDA vendors, where they have contributed to physical verification, density-fill methodology development, process design kits (PDKs), or manufacturing-driven design solutions. 5+ years of hands-on experience developing, deploying, or supporting density fill methodologies for semiconductor technologies at 16nm and below, including ownership of fill rule implementation, density compliance, or manufacturability optimization.