El Segundo, CA30+ days ago
SECRET SECURITY CLEARANCE REQUIRED**Sign on Bonus Eligible*Job Duties:* Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing analysis and closure, verification, and system integration* RTL coding and simulation in VHDL or Verilog* Testbench development for the verification of RTL blocks using VHDL or SystemVerilog* RTL coding and simulation in VHDL or Verilog OR Testbench development for the verification of RTL blocks using UVM and SystemVerilog* Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closureRequired Qualifications: * Due to the nature of the work, U.S. Citizenship is REQUIRED. constrained random, functional coverage, SystemVerilog)* ASIC / FPGA lab validation with advanced lab equipment* Design for Test (DFT) and manufacturability issues* Experience with Unix, scripting, C/C++, and/or Perl* Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g.