NewBusiness Development - Automotive MCUs, Processors and Vehicle Electronic Architectu[...] NXP SemiconductorsBusiness Development - Automotive MCUs, Processors and Vehicle Electronic Architectu[...]San Jose, CAAct as primary interface to OEM and Tier‑1 technical and executive stakeholders (Architects, HW and SW engineers and leaders).Lead customer workshops on vehicle E/E architecture evolution, including zonal controllers, network topology, safety, and compute consolidation. Key ResponsibilitiesDefine and execute the business development strategy for Americas for automotive MCUs, processors, and vehicle compute architectures (zonal / centralized).Identify and drive design‑win opportunities with global automotive OEMs and Tier‑1 suppliers.
CPU/GPU/Processor Hardware Architect Baidu USACPU/GPU/Processor Hardware ArchitectSunnyvale, CaliforniaExperience and knowledge of CPU architecture and deep expertise in one or more areas below but not limited to: ARM/RISC-V/MIPS processors, ISA, Memory subsystem, coherency, AI/ML architecture, security. Good teamwork with communications and support to solve all levels of architecture definition from micro-architecture to system level to software architecture.
Consumer Loan Servicing Processor Jess BusheyConsumer Loan Servicing ProcessorSan Jose, California$64,000This position is responsible for processing servicing requests and loan maintenance related to consumer loans, including vehicles, lines of credit, personal loans, credit cards, and solar. Receives and processes incoming subordination requests by reviewing documents received; prepares the subordination agreement; packages subordination files for review and signature; scans and packages fully executed subordination agreements for mailing.
Processor Advance ServicesProcessorMoss Landing, CASegregate product on conveyor belt or table according to grade, color, and size, and place product in containers or on designated conveyors Gather, weigh and tally roe baskets. Silver Bay Seafoods California processors can be assigned to various positions within the production department including, but not limited to, sorting, boxing, and weighing.
SoC uArchitect / Architect – Automotive, Safety Island, ARM Processor Subsystems and Edge AI Platforms Altera SemiconductorSoC uArchitect / Architect – Automotive, Safety Island, ARM Processor Subsystems and Edge AI PlatformsSan Jose, CaliforniaIn this role, you will contribute to architecture and microarchitecture definition for ARM processor subsystems, safety islands, interconnect fabrics (AXI/APB), memory systems, and FPGA-to-processor integration for edge platforms. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, automotive, and edge.
CPU Processor Performance Verification Engineer Apple IncCPU Processor Performance Verification EngineerSanta Clara, CAWork closely with OS and compiler teams on system and application performance tuningMinimum BS Academic experience with performance modeling, processor verification, or RTL design Academic experience in digital logic design, CPU architecture, and microarchitecture Experience in at least one of the following: assembly, C/C++, Verilog, or System VerilogExperience in developing performance test plans and writing/debugging assembly tests for performance correlation and verification Experience in benchmark and workload analysis and CPU performance profiling Knowledge of compiler techniques and OS for performance optimization Knowledge in developing instruction profiling tools on silicon Experience in performance modeling for advanced CPU designs Experience in silicon validation Ability to work across teams to optimize silicon performance Should be a great teammate with excellent communication and presentation skills and able to work independently on the owned unit. As a CPU Processor Performance Verification Engineer owning the verification of a certain area of performance features in a chip design, you will have responsibilities as follows: Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon).
Embedded Firmware Engineer - Image Signal Processor (ISP) Apple IncEmbedded Firmware Engineer - Image Signal Processor (ISP)Cupertino, CABS or MS in Computer Science, Electrical Engineering, or a related field 3+ years of experience developing multi-threaded software within embedded RTOS environments Strong proficiency in C and C++5+ years of embedded firmware development experience Experience with camera pipelines, image signal processors, or video processing systems Track record of bringing up firmware on new silicon or hardware platforms, Familiarity with pre-silicon development environments including emulators and FPGA prototypes Experience with firmware performance tuning, memory optimization, and power management Proficiency with AI-assisted development tools and workflows Understanding of low-level hardware interfaces and register-level programming Ability to debug complex systems using hardware and software tools Strong communication skills and ability to work effectively across teams. Our team fosters an environment of product innovation, rapid iteration, and collaboration across multiple functions while providing meaningful autonomy to deliver impactful work.
CPU Processor Power Management Verification Engineer Apple IncCPU Processor Power Management Verification EngineerSanta Clara, CAWrite assertions and apply formal verification to the designMinimum BS and 3+ years of relevant industry experience Experience with digital logic, micro-processor architecture, or power management architecture Experience with digital design verification including Verilog/System-Verilog based testbenches and transactors checkers Programming skills in scripting languages such as Perl or PythonMaster's degree preferred Experience in processor or power management architecture and verification In-depth knowledge in design verification environments like random constraint verification and/or UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low power simulation Experience with advanced verification techniques such as formal verification is a plus Advanced programming skills such as object orientated programming or CPU assembly language is a plus Should be an extraordinary teammate with excellent communication skills with the ability to articulate complex design issues during verification effort Be able to create and follow detailed work schedules and work independently on the verification efforts for a block/area of the design. As a CPU Processor Power Management Verification Engineer, you will have the responsibilities as follows: Work closely with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic.
Packet Processor Architect EriduPacket Processor ArchitectSaratoga, CaliforniaInvestigate and resolve complex issues related to packet processing, working closely with cross-functional teams including hardware engineers, firmware developers, and system architects. We are looking for a highly experienced Packet Processor Architect to lead the definition and implementation of Eridu's industry leading Networking ASIC.
Retail Truck Processor (Morning Shift) Marshalls of CARetail Truck Processor (Morning Shift)Sand City, CaliforniaResponsible for delivering a highly satisfied customer experience proven by engaging and interacting with all customers, embodying customer experience principles and philosophy, and maintaining a clean and organized store environment. Accurately rings customer purchases/returns and counts change back to customer according to established operating procedures.
Loan Processor West Coast Community BancorpLoan ProcessorWatsonville, CA$32–$40 / hourWhile performing the duties of this job, the employee may be regularly required to stand, sit, talk, hear, reach, stoop, kneel, and use hands and fingers to operate typical office equipment such as a computer, telephone, mouse and keyboard. West Coast Community Bank is a top-rated community bank with a focus on serving the banking needs of businesses and individuals along the Central Coast, in Silicon Valley and throughout the Bay Area.
Order Processor Yubico IncOrder ProcessorSanta Clara, CA$32–$40 / hourThey will drive operational alignment and take the lead in bridging Sales, Product, Customer Support and Customer Success, Solutions Engineers, Deals Desk, Finance, Production, Planning, Logistics, Inventory and Fulfillment teams to resolve discrepancies, track shipments, and improve order workflows. The Role: We are looking for a Senior Order Processor to process and validate customer orders end-to-end in Salesforce (SFDC), NetSuite and YubiKey as a Service (YaaS) Customer Portal ensuring accurate documentation, products, pricing, payment terms, and timely fulfillment.
Bench Lab Support Tech Envision, LLCBench Lab Support TechSanta Clara, CAMin 2+ years of hands-on experience in an electronic or testing lab in the areas of silicon bring up, board-level design/validation, or system design/validation. Experience with lab test equipment setups for signal measurement using oscilloscopes and understanding to follow a schematic.
Datacenter System Software Architect SiFiveDatacenter System Software ArchitectSanta Clara, CaliforniaSiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. United States of America Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
Senior Director, Architecture Research Lab Samsung SemiconductorSenior Director, Architecture Research LabSan Jose, CA$246,000–$430,000 / yearThe role is responsible for end‑to‑end co‑design of AI workloads, system‑level modeling, hardware platforms, and high‑performance processors that leverage Samsung's advanced memory technologies to eliminate capacity, bandwidth, and large‑scale communication bottlenecks. Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.
Principal Interconnect Design Engineer SiFive IncPrincipal Interconnect Design EngineerSanta Clara, CA$231,444–$282,876 / yearSiFive's unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. Job Description: The Role: SiFive is looking for a principal-level hardware engineer who is passionate about designing industry-leading CPU and interconnect IP to help drive the tidal wave of adoption of RISC-V as the architecture of choice for SOC designs across a broad variety of vertical applications.
Senior Solutions Architect, Datacenter CPUs NVIDIA CorpSenior Solutions Architect, Datacenter CPUsSanta Clara, CAPerformance Tuning & Issue Resolution: We will implement rigorous performance analysis and benchmarking of key cloud workloads, partnering closely with our internal engineering teams to solve complex scalability and reliability issues across the CPU, memory, and networking levels. Together, we will architect and validate multi-tenant cloud infrastructure based on ARM server CPUs, actively influencing reference architectures, our CPU roadmap, and deployment guides to ensure top-tier performance, scalability, and multi-tenancy.
Datacenter System Software Architect SiFive IncDatacenter System Software ArchitectSanta Clara, CA$231,444–$282,876 / yearSiFive's unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
NewSenior Staff Engineer, Electrical Design Celestica IncSenior Staff Engineer, Electrical DesignSan Jose, CA$142,000–$222,000 / yearAs a leader in design, manufacturing, hardware platform and supply chain solutions, Celestica brings global expertise and insight at every stage of product development - from drawing board to full-scale production and after-market services for products from advanced medical devices, to highly engineered aviation systems, to next-generation hardware platform solutions for the Cloud. Celestica is the brand behind the brands you love in tech and we design, develop, and manufacture leading-edge Hardware Platform Solutions in Networking, Storage, and Server solutions from general purpose to customized Cloud, AI, machine learning, Edge and 5G deployments.
NewPrincipal, Design Engineering - Power Celestica IncPrincipal, Design Engineering - PowerSan Jose, CA$142,000–$222,000 / yearAs a leader in design, manufacturing, hardware platform and supply chain solutions, Celestica brings global expertise and insight at every stage of product development - from drawing board to full-scale production and after-market services for products from advanced medical devices, to highly engineered aviation systems, to next-generation hardware platform solutions for the Cloud. Celestica is the brand behind the brands you love in tech and we design, develop, and manufacture leading-edge Hardware Platform Solutions in Networking, Storage, and Server solutions from general purpose to customized Cloud, AI, machine learning, Edge and 5G deployments.
Sr. System Development Engineer, AL/ML/Storage server team Amazon.com IncSr. System Development Engineer, AL/ML/Storage server teamCupertino, CAYou will collaborate with a variety of roles (SDEs, SDETs, Mechanical/Electrical/Hardware Engineers, TPMs, Managers, Principals) and organizations through server conception, test validation, qualification, launch, and operations - driving high quality and reliability into current and future designs for AWS server solutions. You will work across multiple teams and organizations to build scalable, reliable systems that keep our storage and accelerated (AI/ML) compute fleet healthy - with a vision toward zero-touch operations where automation detects, diagnoses, and resolves issues without human intervention.
Design Verification and Emulation Manager Efficient ComputerDesign Verification and Emulation ManagerSan Jose, PennsylvaniaThis role combines deep technical expertise with strong people leadership and program execution skills, and is ideal for someone who thrives at the intersection of architecture, verification methodology, hardware-software integration, and team building. SoC Architecture: Solid understanding of modern SoC architectures — processors (ARM, RISC-V), cache coherency, interconnects (AMBA AXI/ACE/CHI), memory subsystems, and common peripherals.
Principal Engineer, ASIC Design Verification Ayar Labs IncPrincipal Engineer, ASIC Design VerificationSan Jose, CA$190,000–$240,000 / yearBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Strategic Planning: Collaborate with Architects and RTL Designers early in the cycle to define the verification plan, identify architectural bottlenecks, and ensure micro-architecture testability.
Senior Technical Staff Engineer - Validation (System Design) Microchip Technology IncSenior Technical Staff Engineer - Validation (System Design)San Jose, CA$91,000–$232,000 / yearOur product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). Hands-on systems level design and debug experience with following high-speed serial communications protocols (must: PHY, PCS and Data link layer of the OSI protocol stack; desirable: transaction and upper layers of the OSI protocol): Protocol Testing at UNH for various IEEE Clauses pertaining to.
Sr. Director, Indirect Procurement d-Matrix CorpSr. Director, Indirect ProcurementSanta Clara, CAEngineering Lab & Hardware Equipment: Procure lab hardware for AI inference development (servers, GPUs, FPGAs, test cards, rack infrastructure) and test/measurement equipment from vendors such as Keysight and Tektronix. The ideal candidate brings deep expertise in contract negotiation, vendor management, and IP licensing within a semiconductor or AI hardware environment, and is comfortable building scalable procurement infrastructure in a high-growth startup.
Technical Staff Engineer - Applications Microchip Technology IncTechnical Staff Engineer - ApplicationsSan Jose, CA$91,000–$232,000 / yearOur product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). Advanced level domain expertise in one or more FPGA/SoC design/debug expertise - DDR memory interfaces and protocols, Transceiver and high speed serial interfaces, timing closure techniques, FPGA synthesis and simulation, Embedded Cortex or RISC-V processor/microcontrollers etc, Serdes and high-speed serial interfaces and protocols.
Digital Hardware Engineer Apple IncDigital Hardware EngineerSunnyvale, CAHands-on hardware debugging expertise, including the use of modern lab equipment (DSOs, logic analyzers, protocol analyzers), with prior experience in PCIe PHY validation being highly advantageous. Drive volume stress testing and system-level validation of wireless chipsets (internal and vendor-supplied) using production firmware across multiple hardware configurations.
Hardware Design Engineer Apple IncHardware Design EngineerSunnyvale, CAProven track record of leading project teams to complete projects or key components of the project 5+ years of experience delivering consumer electronic products is preferred Experience in architectural discussion with cross-functional leaders related to Power supply and Digital design for the connectivity HW and able to influence product direction for these designs Experience with power supply/power management Hands on debug experience with usage of modern lab equipment (DSOs, Logic Analyzers, Protocol Analyzers) Experience in writing basic software routines and test scripts Strong desire to investigation system level issues and drive problems to closure in a team-based environment with a proactive demeanor Experience with mobile and/or embedded processors and memory systems Experience with schematic capture/layout Experience interacting with offshore manufacturing partners Successful track record of delivering highly innovative communications products Experience with high volume, low power, mobile products. Implement in-product schematics and layout Work with internal hardware and silicon teams to bring-up, characterize (performance/power) and validate new digital interfaces + protocols Work with power supply application circuit design and validation, including load step response, ripple and accuracy, stability Work with external chipset vendors to develop successful integration and verification plans Be required to travel internationally as needed (~15%)BS and 10+ years of relevant industry experience Good understanding of protocol specifications for communication interfaces like PCIe, MIPI, I2C, SPI, UART, etc.
Senior Digital Design Engineer, IP and Methodology Astera Labs IncSenior Digital Design Engineer, IP and MethodologySan Jose, CA$135,000–$195,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Optical Firmware Engineer, Principal Astera Labs IncOptical Firmware Engineer, PrincipalSan Jose, CAAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Senior Staff Firmware Engineer Marvell Technology IncSenior Staff Firmware EngineerSanta Clara, CAThese solutions address all segments of the hard disk drive (HDD) and solid-state drive (SSD) electronics markets, providing complete solutions including controllers, product firmware, and reference board designs. This position is for the optics DCI (Data Center Interconnect) Firmware team which develops embedded software for Marvell''s high speed coherent fiber transceivers used for scale across communication, moving data between data centers worldwide.
Principal Digital Design Engineer Astera Labs IncPrincipal Digital Design EngineerSan Jose, CA$185,000–$230,000 / yearYoull own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the worlds leading hyperscalers.
Hardware Product Application Engineer Advanced Micro Devices IncHardware Product Application EngineerSanta Clara, CACo-develop technical collateral, such as application note, user guide, sample, and reference design materials • Engage directly on key technical topics, issues, architecture discussions, and performance optimizations with customers and internal teams • Collaborate seamlessly across domains including platform and silicon engineering, product management, and field application engineering. Those includes delivering necessary trainings, answering any inquires, creating collaterals, reviewing design files, and debugging issues, working with internal teams.
Sr. ASIC Verification Engineer Recogni IncSr. ASIC Verification EngineerSunnyvale, CAResponsibilities: Your responsibilities will be wide-ranging and and run the gamut of working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular SystemVerilog and UVM, handling bug tracking and coverage convergence and developing scripts and methodologies for the front-end ASIC flow. This ASIC's design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to deliver the high-performance multi-chip silicon solutions that are at the heart of Tensordyne's vertically integrated, generative AI inference acceleration systems for data centers.
Design Verification and Emulation Manager EfficientAI CorpDesign Verification and Emulation ManagerSan Jose, CA$210,000–$250,000 / yearKey ResponsibilitiesDefine end-to-end verification strategy from block-level through full-chip simulation to emulation and prototypingOwn UVM-based methodology, including constrained-random, coverage-driven closure, assertions, and formal verification adoptionDrive emulation platform strategy - platform selection, capacity planning, compilation flows, and multi-project schedulingEnable system-level validation on emulation - processor boot, OS bring-up, firmware execution, and IO exercisingDeliver pre-silicon platforms for early software development in partnership with firmware and software teamsEstablish hybrid simulation-emulation methodologies using transactor-based interfaces to maximize both environmentsOwn functional coverage models and sign-off criteria, driving closure across simulation and emulation combinedLead debug and root cause analysis across simulation and emulation, driving cross-functional bug resolutionManage verification dashboards, bug tracking, and regression health to provide clear visibility to program leadershipBuild, mentor, and scale a high-performing team of verification and emulation engineersDrive verification schedules and risk mitigation aligned with chip program milestones and tapeout readinessRepresent verification and emulation in tapeout readiness reviews and program-level decision forumsCollaborate cross-functionally with Compiler Team, RTL design, architecture, DFT, physical design, and post-silicon teamsManage emulation lab infrastructure, including hardware resources, licensing, and vendor relationshipsEvaluate and adopt new EDA tools and methodologies, including AI/ML-assisted verification techniques. This role combines deep technical expertise with strong people leadership and program execution skills, and is ideal for someone who thrives at the intersection of architecture, verification methodology, hardware-software integration, and team building.
Sr. Staff ASIC Verification Engineer Recogni IncSr. Staff ASIC Verification EngineerSunnyvale, CAResponsibilities: Your responsibilities will be wide-ranging and and run the gamut of working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular SystemVerilog and UVM, handling bug tracking and coverage convergence and developing scripts and methodologies for the front-end ASIC flow. This ASIC's design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to deliver the high-performance multi-chip silicon solutions that are at the heart of Tensordyne's vertically integrated, generative AI inference acceleration systems for data centers.
Solutions Architect Advanced Micro Devices, IncSolutions ArchitectSan Jose, CaliforniaParticipate in a technical role in all phases of the product development cycle from new product exploration, architecture through implementation, prototyping, validation, productization and support including but not limited to architecture, design, and documentation for IPs. Join our team to architect and develop cutting-edge hardware/software co-design solutions for FPGA-based acceleration across a wide range of applications—such as networking, storage, automotive, aerospace, and emerging AI/ML workloads.