We are seeking a Senior Verification Engineer to play a key role in the development of next-generation ASIC and SoC products, driving verification strategy and execution from IP-level components through full system integration. In this role, you will develop verification plans, build robust SystemVerilog/UVM and formal verification environments, define coverage goals, debug complex digital designs, and ensure functional correctness through sign-off. You will collaborate closely with design, architecture, and modeling teams while helping establish verification methodologies, infrastructure, and best practices for a growing silicon program. The ideal candidate brings strong experience in ASIC or SoC verification, metric-driven verification methodologies, assertion-based verification, and complex datapath and control logic validation. Success in this role requires excellent analytical and problem-solving skills, a systems-level mindset, and the ability to drive verification efforts in a fast-paced development environment. Experience with formal verification, high-performance computing, communications systems, DSP, networking, AI-assisted verification tools, or advanced SoC architectures is highly desirable.
Compensation: $120.00/hr
We look forward to reviewing your application. We encourage everyone to apply - even if every box isnt checked for what you are looking for or what is required.
PDSINC, LLC is an Equal Opportunity Employer.