Design Verification

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldnt have imagined, and now, cant imagine living without. Its the diversity of those people and their ideas that inspires the innovation that runs through everything we do. APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Review specifications of Mixed Signal Blocks (such as Analog-Digital Convertor, Phase-locked Loop, etc.), extracting features of signals, defining, and executing verification plan. Develop top/block level Mixed Signal and Digital testbench and generating directed/ constrained-random tests in a UVM (Universal Verification Methodology) framework. Develop checkers/assertions in System Verilog, a hardware description language, to capture incorrect signal behaviors in circuit simulations such as seeing unexpected signal values or sequences from those in documented specifications. Validate the correctness and robustness of models by analyzing the waveforms in Xcelium tool and comparing simulation results of SPECTRE models with results of System Verilog models. Debug failures of circuit simulation tests with waveforms and analyze errors reported by checkers; fix testbench/model/checker and design issues; track bug resolutions. Track and analyze functional coverages of all signals with vManager tool to make sure all functional behaviors are covered in all tests. Write scripts for automation of flow in Python language, such as auto-generating checkers with design specifications documents, parsing and auto-capturing typos in circuit model files. Extract information from design documents and schematics of circuits. Based on the information develop digital mixed-signal behavioral model written in system-verilog or Verilog language to represent the analog circuits. Maintain the config of Virtuoso Hierarchy Editor, use it to generate the netlist for design verification. Work closely with analog and digital designer, verification peers and DFT engineers to debug simulation failures to ensure that the circuitry's functions are correct. Summarize and document simulation results; hold review meetings with analog circuit designers and digital designers. Coordinate with different designers to sign-off the simulation results. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.Bachelor's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or related field and 1 year of experience in the job offered or related occupation. Experience and/or education may include:

Using knowledge of electrical circuits, analyzing functions of analog blocks such as Current Mirror and Amplifier, and understanding of logic gates of digital blocks. Working with SOC architecture or computer architecture. Using Verilog and System-Verilog language to write RTL modules and behavioral models. Using UVM (universal verification methodology) to develop test sequence and testbench components for design verification. Utilizing Python or Perl to develop scripts or tools to aid verification works. Using Cadence Virtuoso tool to compose and navigate schematic of circuit. Using Virtuoso Hierarchy Editor to configure the design and create netlist. Using EDA tools including Xcelium, Simvision and Indago to work on the design verification. Experience using industry standard protocols such as I2C, SPI, or AHB. Experience of working in Unix or Linux environment, can write shell scripts for BASH, CSH or TCSH. Using Microsoft Office Tools suite or Apple Pages, Numbers and Keynotes to document technical specifications and give presentations.N/A