This position offers a great opportunity to work on industry leading semiconductor devices, targeted for broad applications in Automotive and Industrial markets. In this role, you'll be a member of DfT and Technology Development team, driving Design-for-Test (DfT) and Built-in Self-Test (BiST) technologies and solutions for analog, mixed signal and digital circuits for current and new IPs. Knowledge of analog / mixed signal blocks, DFT, analog and digital test methodologies and HW design requirements and care-abouts are critical skillsets needed to be successful in this role. End goal is to design and productize deep analog and mixed signal test solutions that are high in efficiency (low cost, and high coverage), enabling organization benchmarks in cost-of-test and quality goals.
onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world's most complex challenges and leads the way in creating a safer, cleaner, and smarter world.
More details about our company benefits can be found here:
https://www.onsemi.com/careers/career-benefits
- BSEE with minimum 5+ years of direct experience of Analog / NVM / High Speed IO Digital Test & DFT Design knowledge
- Experience working with ATE platforms.
- Good programming skills using C/C++, Perl, Python
- Strong statistical data analysis skills including correlation and application to test optimization
- Excellent communication and leadership skills, working with cross-functional teams across multiple different internal development and factory sites.
- Extensive knowledge and hands-on experience with DFT methodologies, including scan, MBIST, JTAG, analog BIST, ATPG, functional test, and test compression.
- Experience in implementation of MBIST for memories and knowledge of repair schemes, algorithms
- Excellent interpersonal skills - energetic, motivated, and self-driven
- Demonstrate ability to work well within a global team environment.
- Outstanding written and verbal communication skills
- Strong organizational skills and demonstrate ability to manage multiple tasks.
As a member of the "DfT and Technology Development" Product Engineering Team, you will be required to own, participate, lead, and drive below activities:
- Definition of Design-for-Test (DfT) and Built-In-Self-Test (BIST) techniques for complex analog and digital designs working with design team.
- Identify and deploy company's DFT/DFx standards and practices with a focus on improved quality and cost reduction.
- Develop and implement DFT methodologies and strategies for mixed-signal designs.
- Collaborate with cross-functional teams to ensure proper integration of DFT features into the overall design.
- Candidate is also expected to participate in Product DFT/Design Reviews prior to device fabrication (pre-TO/PG) to define and outline ATE resource allocation, understand product spec requirements, outline test plan and project test times and requirements keeping in mind ATE HW limitations and capabilities.
- Define and propose ATE solutions through "out-of-the-box" thinking during the product development. Drive for test solutions with maximal DfT and minimal test complexity (both hardware and software).
- Align test plans with BU PE and design teams to define DFT requirements, test methods and checklists.
- You will be a member of a cross-functional team working on complex ATE testers (Advantest, Teradyne) to drive low cost-of-test solutions for complex analog and digital IPs, in high volume production testing.
- Having additional knowledge of power management, digital interfaces (SPI, DS3, CAN, I3C etc.) and digital test interfaces (Scan modes, JTAG, iJTAG, SWD,etc.), RF testing, massive multi-site test, and/or devices requiring safety & security, JTAG/iJTAG/P1500 networks, ICL and PDL is considered a HUGE PLUS. The candidate, in this role, is expected to learn protocols and industry standards for these interfaces and IPs, define test methods for high-volume production testing with high parallelism, and build / code ATE test-plans for characterization and production testing.
- Drive defect-based test methods for production and qualification (ATPG, stress, high resolution leakage screening, etc.).
- Architect hierarchical DFT solutions covering multiple clock and power domains
As a member of the "DfT and Technology Development" Product Engineering Team, you will be required to own, participate, lead, and drive below activities:
- Definition of Design-for-Test (DfT) and Built-In-Self-Test (BIST) techniques for complex analog and digital designs working with design team.
- Identify and deploy company's DFT/DFx standards and practices with a focus on improved quality and cost reduction.
- Develop and implement DFT methodologies and strategies for mixed-signal designs.
- Collaborate with cross-functional teams to ensure proper integration of DFT features into the overall design.
- Candidate is also expected to participate in Product DFT/Design Reviews prior to device fabrication (pre-TO/PG) to define and outline ATE resource allocation, understand product spec requirements, outline test plan and project test times and requirements keeping in mind ATE HW limitations and capabilities.
- Define and propose ATE solutions through "out-of-the-box" thinking during the product development. Drive for test solutions with maximal DfT and minimal test complexity (both hardware and software).
- Align test plans with BU PE and design teams to define DFT requirements, test methods and checklists.
- You will be a member of a cross-functional team working on complex ATE testers (Advantest, Teradyne) to drive low cost-of-test solutions for complex analog and digital IPs, in high volume production testing.
- Having additional knowledge of power management, digital interfaces (SPI, DS3, CAN, I3C etc.) and digital test interfaces (Scan modes, JTAG, iJTAG, SWD,etc.), RF testing, massive multi-site test, and/or devices requiring safety & security, JTAG/iJTAG/P1500 networks, ICL and PDL is considered a HUGE PLUS. The candidate, in this role, is expected to learn protocols and industry standards for these interfaces and IPs, define test methods for high-volume production testing with high parallelism, and build / code ATE test-plans for characterization and production testing.
- Drive defect-based test methods for production and qualification (ATPG, stress, high resolution leakage screening, etc.).
- Architect hierarchical DFT solutions covering multiple clock and power domains