Elect Design and Analy Engr 4 - Microelectronics - CA

Artech LLC

  • Mountain View, CA
  • Today
  • $70–$80 Per Hour
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Skills

  • ASIC (Application Specific Integrated Circuit)unmatched
  • ASIC Verificationunmatched
  • Avionicsunmatched
  • Centers for Disease Control and Prevention (CDC)unmatched
  • Code Coverageunmatched
  • Customer Experienceunmatched
  • Debugging Skillsunmatched
  • Emulatorsunmatched
  • Ethernetunmatched
  • FPGAunmatched
  • Gitunmatched
  • Hardware Quality Assuranceunmatched
  • IP (Internet Protocol)unmatched
  • Integration Testingunmatched
  • Linux Operating Systemunmatched
  • Object Oriented (OO)unmatched
  • PCI Express (PCI-E)unmatched
  • Perl Programming Languageunmatched
  • Prototypingunmatched
  • Python Programming/Scripting Languageunmatched
  • SERDESunmatched
  • Scripting (Scripting Languages)unmatched
  • Sequencersunmatched
  • Source Code/Configuration Management (SCM)unmatched
  • Static Timing Toolsunmatched
  • Subversionunmatched
  • SystemVerilogunmatched
  • Test Plan/Scheduleunmatched
  • Verification Engineeringunmatched

Description

Job Title: Elect Design and Analy Engr 4

Location: Mountain View, CA

Salary Range: $80 - $90/hour

Competitive and commensurate with experience

Introduction

Join our dynamic team focused on Electronic Products — ASICs & FPGAs for Space, Avionics, and Defense. We are seeking a skilled ASIC/FPGA Verification Engineer with expertise in UVM/SystemVerilog to contribute to our cutting-edge projects.

Required Skills & Qualifications

  • Bachelor’s degree in EE, CE, CS, or related field (or equivalent experience).
  • Experience with ASIC/FPGA verification using SystemVerilog and UVM.
  • Ability to build self-checking testbenches and use object-oriented SV features.
  • Familiarity with functional coverage and code coverage closure.
  • Comfortable in Linux and using scripting tools.
  • Must have previous client experience working for this customer in the past 5 years.

Preferred Skills & Qualifications

  • 2 years (Associate) or 5 years (Experienced) verification experience.
  • Experience with hardware emulators (e.g., Palladium) and FPGA prototyping.
  • Knowledge of high-speed SerDes (PCIe, Ethernet, JESD204C).

Day-to-Day Responsibilities

  • Write SystemVerilog/UVM testbenches to verify ASICs and FPGAs.
  • Develop self-checking, reusable UVM components: drivers, monitors, scoreboards, sequencers.
  • Build functional coverage models and close code coverage gaps.
  • Create tests that verify DSP and third-party IP integration.
  • Run simulations, linting, CDC checks, static timing checks, and gate-level regressions.
  • Use scripting (Python/Perl/Make) and revision control (git/svn) to automate flows.
  • Support FPGA bring-up, hardware emulation/prototyping, and hardware integration tests.
  • Collaborate with system and hardware teams to capture requirements and debug issues.

Company Benefits & Culture

  • Comprehensive health insurance plans.
  • Flexible work hours and remote work options.
  • Opportunities for professional development and career growth.

For immediate consideration please click APPLY to begin the screening process with Alex.

saksham.srivastava@artech.con

Numbers & Facts

LocationMountain View, CA
Salary$70–$80 Per Hour

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