Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise. 10+ years of hands-on custom IC layout experience as a senior individual contributor (this is not a lead/people-management role), including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.