Job Description
JD for PD:
- Exposure to TSClient 2NP/3NP is must
- Perform end to end physical design flow:
- Floorplanning
- Power planning (PG grid, IR)
- Placement & optimization
- CTS (Clock Tree Synthesis)
- Routing
- Post route optimization
- Achieve timing closure across all modes and corners
- Resolve DRC, LVS, ERC and signoff violations
- Handle low power design techniques:
- Multi Vt, Multi voltage (UPF)
- Power gating, clock gating
- Perform physical verification and signoff:
- STA (Primetime)
- SI / Crosstalk
- IR drop & EM analysis
- Work on advanced nodes (7nm, 5nm, 3nm or below)
- Collaborate with:
- RTL & Micro architecture teams
- DFT & Test engineers
- Foundry and CAD teams
- Debug complex timing, congestion, power, and variability issues
- Drive methodology improvements and automation (scripts/flows)
Numbers & Facts
| Location | Palo Alto, CA, CA |
| Industry | Other/Not Classified |
| Company Size | 100 to 499 employees |
| Year Founded | 1998 |
| Website | www.eteaminc.com |
About Company
Looking for a great job? Join eTeam. We’re looking for talented staffing professionals to join our staff. We also provide contract assignments and full-time jobs at Fortune 2000 Companies. We’ve been named one of the best companies to work for by Staffing Industry Analysts and New Jersey Business.
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