Position would require the candidate to be a W2 employee of Donatech,
US Citizenship Required.
Active Secret Clearance Required.
-Adhere to all applicable client Engineering Development and Quality processes, procedures, instructions and guidelines.
-Participate in Agile team meetings and planning activities, as required to support programs covered by this work plan.
-Requirements capture, development, and implementation of signal processing algorithms for FPGA or ASIC based systems.
-Utilize Simulink for modeling and simulation of signal processing systems and workflows.
-Collaborate with cross-functional teams to integrate signal processing solutions into larger systems
-Optimize FPGA implementations to meet performance, power, and size constraints.
-Conduct system-level analysis and testing to ensure adherence to project requirements.
-Supporting peer reviews and certification analysis activities
-Peer reviewing FPGA development artifacts
-Management of change request and task assignments through Jira
Qualifications You Must Have
-Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 5 years prior relevant experience or an Advanced Degree in a related field and minimum 3 years of experience.
-An active U.S. government issued Final Secret Security Clearance is required
-A minimum of 3 years professional experience in FPGA development, ASIC front end, or related areas
-Professional experience in signal processing, FPGA/ASIC development, or related areas
-Demonstrated experience developing signal processing solutions using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
-Expertise in Simulink and/or MATLAB for modeling and simulation of DSP systems
-Proficient in VHDL/Verilog for FPGA/ASIC design and implementation
-Demonstrated experience with algorithm development for signal processing applications such as filtering, modulation, demodulation, and spectral analysis
-Proficient in VHDL/Verilog for FPGA/ASIC design and implementation.
-Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure
-Familiarity with FPGA platforms such as AMD/Xilinx, Altera, Microchip, or others, and associated toolchains (e.g., Vivado, Quartus, Libero).
-Strong debugging and troubleshooting skills for FPGA/ASIC systems.
-Proficiency with revision control concepts and tools (e.g., Git, Subversion)
Qualifications We Prefer
-Excellent communication and teamwork skills with the ability to work in a collaborative environment.
-Experience with high-speed digital interfaces and protocols (e.g., DDR, PCIe, Ethernet)
-Familiarity with HDL Coder and generation of HDL from model-based designs
-Familiarity with best-practice chip-level verification techniques and languages (e.g., constrained random, functional coverage, System Verilog)
-Experience in Simulink and/or MATLAB for modeling and simulation of DSP systems
-Experience with algorithm development/implementation for signal processing applications such as filtering, modulation, demodulation, and spectral analysis
-Experience in ASIC / FPGA lab validation using advanced laboratory equipment
-Experience with Unix, scripting, C/C++, and/or Perl