Senior Physical Design Engineer

Job Title: Senior Physical Design Engineer

Location: Sunnyvale, CA

Job Type: Full-time

Work Arrangement: Onsite role, Work from Client Office – 5 days a week

Interview: Two rounds of Video interview

Job Description:

Key Responsibilities

• Drive RTL synthesis and optimization to achieve performance, power, and area (PPA) goals

• Perform floor planning for complex ASIC/SoC designs while ensuring optimal timing, congestion, and power distribution

• Collaborate closely with RTL design engineers to provide actionable feedback that improves RTL quality, synthesis results, and overall implementation

• Analyze netlists and identify opportunities for optimization to improve design quality and implementation efficiency

• Work cross-functionally with architecture, RTL, verification, and physical design teams to ensure smooth design convergence

• Support timing closure by identifying implementation bottlenecks and recommending design improvements

• Participate in design reviews and contribute to continuous process and methodology improvements

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field

• Strong hands-on experience in ASIC/SoC physical design with 10+ years of industry experience.

• Expertise in RTL synthesis and timing optimization

• Solid experience with floor planning for advanced technology nodes

• Strong understanding of netlist optimization and physical implementation methodologies

• Experience collaborating with RTL/design teams to improve design quality and implementation efficiency

• Excellent communication and cross-functional collaboration skills

Preferred Skills

• Experience with industry-standard EDA tools for synthesis and physical design

• Strong understanding of timing, congestion, power, and area optimization techniques

• Experience working on high-performance CPU, GPU, AI/ML, or networking SoCs is a plus