Senior Physical Design Engineer, FullChip/ASIC Implementation

Senior Physical Design Engineer, FullChip/ASIC Implementation

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corporate_fareGoogleplaceMountain View, CA, USA

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Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

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XIn most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications:

• Bachelors degree in Electrical Engineering or equivalent practical experience.

• 8 years of physical design experience

• Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).

• Experience in high performance synthesis, PnR, sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.

Preferred qualifications:

• Experience in top-level floorplanning, block integration.
• Experience in low power design Implementation including UPF/CPF, multi-voltage domains, power gating.
• Experience with ASIC design flows and methodology of Physical design.
• Knowledge of fundamentals of computer architecture and of Verilog/SystemVerilog.
• Understanding of Circuit design, device physics and deep submicron technology.
• Exceptional skills with scripting languages such as Tcl, or Perl.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Googles direct-to-consumer products. Youll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Googles mission is to organize the worlds information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make peoples lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Develop all aspects of ASIC Register Transfer Level to Graphic Data System (RTL2GDS) implementation for high Power, Performance, and Area (PPA) designs.
• Manage full-chip level physical implementation.
• Define and implement innovative schemes to improve Performance and Power.
• Work with cross functional teams to deliver best Quality of results.

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Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Googles EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

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