Senior Physical Design Engineer

Pay Range: $66.42hr - $71.42hr

Job Overview:

This is a Physical Design Engineering role that will require taking the design from RTL to GDS with synthesis, Place and Route, timing, and Physical Verification.

Candidate Profile:

The candidate should possess strong communication skills, the ability to multi-task across projects, and experience working with geographically spread-out teams.

Responsibilities:

The engineer will work on leading-edge technology node designs. This includes automated synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control logic applications, automated design flows for clock tree synthesis, clock gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. The candidate will also support floor planning, establishing design methodology, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.

Preferred Skill Sets:

• Major in EE, CS, or related field with a Master's degree and 3+ years of experience, or a Bachelor's degree with 5+ years of working experience, preferably with high-speed designs or other high-performance IP designs.
• Experience in automated synthesis and timing-driven place and route of RTL blocks (Verilog experience preferred) for high-speed datapath and control logic applications, mainly using ICC2, Fusion Compiler, Calibre, and PrimeTime.
• Experience in automated design flows for clock tree synthesis, clock gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
• Strong background in digital circuit techniques, efficient and robust implementation topologies for logic functions, logic optimization, and transistor-level circuit topologies for high-speed, low-power applications.

Education:

Major in EE, CS, or related field with a Master's degree preferred, focusing on high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs.