Senior Staff Verification Consultant

• Lead and maintain gate-level simulation (GLS) flows and run GLS regressions and timing/SDF validation.
• Execute power-aware verification using UPF and integrate UPF flows into GLS and verification regressions.
• Debug functional and timing failures at gate-level and recommend/approve design fixes when necessary.
• Collaborate closely with local verification and design stakeholders in Austin or San Jose to resolve IP-level issues.
• Work heavily on CHI/interconnect and AXI protocol verification and provide guidance on adjacent interconnect protocols (ACE-Lite, APB).
• Analyze simulation results, coverage, and waveform data to drive closure and report status to stakeholders.
• Automate GLS and UPF runs with scripting and version-control best practices.

• 12+ years industry experience in a design verification role.
• 5+ years hands-on experience with gate-level simulations and timing/SDF validation.
• Hands-on experience running UPF / power-aware simulations.
• Strong experience with CHI and AXI protocols; familiarity with ACE-Lite and APB.
• Proficient with SystemVerilog (testbenches, assertions) and verification methodologies.
• Experience with Git, Unix/Linux, and scripting in Perl and/or Python.
• Excellent collaboration and communication skills; able to drive complex debug with design teams.

• Background in high-performance computing or experience at companies focused on HPC/data-center SoCs (example experience: Qualcomm, Microsoft, major server SoC vendors).
• Prior experience maintaining large GLS flows (tool knowledge such as VCS, Xcelium, QuestaSim, or similar).
• Experience working in mixed-location teams with offshore SoC teams.

waseem.ahmad@leadstackinc.com