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Job Title: Senior Staff Verification Consultant — Gate-Level / Power-Aware Verification
Duration: 6 months (strong possibility to extend)
Location: Austin, TX/ San Jose, CA — onsite 5x/week
Overview
We are seeking a senior-level Design Verification engineer with 12+ years of experience in verification and a strong, hands-on background in gate-level simulation and power-aware verification. The ideal candidate will own gate-level simulation activities, run UPF (power-aware) simulations, and work closely with design and verification teams on CHI/interconnect and AXI protocol IP. This role sits on a verification team of 16 engineers (mix of junior and senior); the SoC team is offshore and will not be a primary interface. The hire will not be expected to build GLS flows from scratch but will maintain existing GLS flows, perform deep debug, and approve design changes where required.
Key responsibilities
Lead and maintain gate-level simulation (GLS) flows and run GLS regressions and timing/SDF validation.
Execute power-aware verification using UPF and integrate UPF flows into GLS and verification regressions.
Debug functional and timing failures at gate-level and recommend/approve design fixes when necessary.
Collaborate closely with local verification and design stakeholders in Austin or San Jose to resolve IP-level issues.
Work heavily on CHI/interconnect and AXI protocol verification and provide guidance on adjacent interconnect protocols (ACE-Lite, APB).
Analyze simulation results, coverage, and waveform data to drive closure and report status to stakeholders.
Automate GLS and UPF runs with scripting and version-control best practices.
Must-have qualifications
12+ years industry experience in a design verification role.
5+ years hands-on experience with gate-level simulations and timing/SDF validation.
Strong experience with CHI and AXI protocols; familiarity with ACE-Lite and APB.
Proficient with SystemVerilog (testbenches, assertions) and verification methodologies.
Experience with Git, Unix/Linux, and scripting in Perl and/or Python.
Excellent collaboration and communication skills; able to drive complex debug with design teams.
Nice-to-have
Background in high-performance computing or experience at companies focused on HPC/data-center SoCs (example experience: Qualcomm, Microsoft, major server SoC vendors).
Prior experience maintaining large GLS flows (tool knowledge such as VCS, Xcelium, QuestaSim, or similar).
Experience working in mixed-location teams with offshore SoC teams.
know more about current opportunities at LeadStack , please visit us on https://leadstackinc.com/careers/
Should you have any questions, feel free to call me on (513) 3184502 or send an email on