Sr. Staff Engineer - Digital Design Verification

Ambiq Micro
  • Austin, Texas
    30+ days ago

    Job Description

    Company Overview

    Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.

    Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.

    Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.

    We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.

    At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.

    If that's you, join us — the intelligence everywhere revolution starts here.

    Responsibilities

    You will be responsible for verifying complex digital designs, including Systems-on-Chip (SoCs) with multiple CPUs, digital signal processors, security hardware, interconnects, and peripheral logic supporting IoT and edge-compute applications.

    The ideal candidate is a self-starter who takes full ownership of verification efforts and consistently delivers high‑quality, production‑ready silicon.

    Key responsibilities include:

    • Own and execute end-to-end digital verification at block, sub-system, and full-chip (SoC) levels
    • Develop detailed verification plans aligned with architecture and design specifications
    • Perform SoC-level verification using full-chip simulation and regression environments
    • Architect and implement scalable, reusable UVM-based testbenches using SystemVerilog
    • Develop comprehensive test scenarios, stimulus, monitors, and checkers to achieve robust functional coverage
    • Drive constrained-random and directed testing, including scoreboarding and self-checking mechanisms
    • Develop and maintain C/C++ based verification libraries and tests for SoC-level validation
    • Automate verification flows for regressions, coverage collection, and results reporting
    • Define, track, and close functional and code coverage goals
    • Utilize advanced debugging methodologies to isolate and resolve complex design and verification issues
    • Perform root-cause analysis and collaborate closely with design teams to drive fixes
    • Ensure verification quality meets or exceeds project, schedule, and industry standards

    Experience with edge-based AI inference workloads is a plus.

    Requirements

    • BSEE or MSEE with 8–12 years of hands-on digital design verification experience
    • Proven track record of multiple tape-outs with silicon functioning to specification
    • Strong experience in block-level, sub-system, and full-chip SoC verification
    • Ability to define and manage verification deliverables, milestones, and schedules
    • Proactively identify verification risks and implement mitigation strategies
    • Experience working with complex SoCs integrating multiple 3rd-party IPs and VIPs
    • Strong collaboration skills to work effectively with design, architecture, and software teams
    • Excellent communication skills for reporting status, issues, and progress to stakeholders

    Technical Skills

    • Design Verification:
      • SystemVerilog, UVM, Verilog
      • Functional and code coverage methodologies
      • Constrained-random verification and scoreboarding
    • SoC & Software-Based Verification:
      • C/C++ based verification in SoC environments (required)
      • Experience with processor-based systems (ARM and/or RISC‑V preferred)
    • Architectures & Protocols:
      • ARM or RISC‑V processor-based SoCs
      • AMBA protocols (AXI, AHB, APB)
      • DMA, flow control, and standard serial interfaces
    • Scripting & Automation:
      • Python, Perl, Makefile
    • Low Power (Digital):
      • Experience verifying low-power digital architectures and features is highly desirable

    Preferred Experience

    • Security IPs (Crypto, OTP)
    • DSP and compute-heavy digital subsystems
    • High-performance or low-power SoC architectures
    • Edge AI / ML workload enablement

    Must be currently authorized to work in the United States for any employer. 

    Numbers & Facts

    LocationAustin, Texas

    Skills

    • ARM (Advanced RISC Machine)unmatched
    • Artificial Intelligence (AI)unmatched
    • C Programming Languageunmatched
    • C++ Programming Languageunmatched
    • CPU (Central Processing Unit)unmatched
    • Code Coverageunmatched
    • Communication Skillsunmatched
    • Cryptographyunmatched
    • Debugging Skillsunmatched
    • Delivery Managementunmatched
    • Design Verificationunmatched
    • Digital Circuit Designunmatched
    • Digital Signal Processing (DSP)unmatched
    • Electrical Engineeringunmatched
    • Energy Efficiencyunmatched
    • Graphic Designunmatched
    • Industry Standardsunmatched
    • Internet of Thingsunmatched
    • Intrusion Prevention Systemsunmatched
    • Low Powerunmatched
    • Make Compilation Utilityunmatched
    • Medical Equipmentunmatched
    • Perl Programming Languageunmatched
    • Problem Solving Skillsunmatched
    • Project Scheduleunmatched
    • Python Programming/Scripting Languageunmatched
    • RISC Processorsunmatched
    • Requirements Managementunmatched
    • Risk Analysisunmatched
    • Risk Managementunmatched
    • Root Cause Analysisunmatched
    • Scripting (Scripting Languages)unmatched
    • Semiconductorsunmatched
    • Serial Link Designunmatched
    • Simulationunmatched
    • Software Architecture Designunmatched
    • System-on-a-Chip (SoC)unmatched
    • SystemVerilogunmatched
    • Team Playerunmatched
    • Test Plan/Scheduleunmatched
    • Test Scenariounmatched
    • Testingunmatched
    • Verification Plansunmatched
    • Verilog Hardware Description Languageunmatched
    • Wearablesunmatched

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