SRAM Layout Design Engineer/Design Engineer

Required Qualifications
BSEE or equivalent experience.
10+ years of hands-on custom IC layout experience as a senior individual contributor (this is not a lead/people-management role), including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
Hands-on, personal ownership of custom digital SRAM layout — candidates must have directly executed the layout themselves, not simply overseen or reviewed it. This role is not a fit for mixed-signal or analog layout backgrounds.
Hands-on experience at TSMC 3nm or a more advanced process node. Experience limited to 10nm or 7nm does not meet the bar for this role; 5nm is a plus, but 3nm is the minimum.
Solid grasp of SRAM and memory layout principles.
Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.
Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.