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TPU RTL Design Engineer

Google

Sunnyvale, CA

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JOB DETAILS
SKILLS
ASIC (Application Specific Integrated Circuit), ASIC Design, Artificial Intelligence (AI), Cloud Computing, Computer Architecture, Computer Engineering, Computer Science, Control Systems, Data Analysis, Debugging Skills, Design Verification, Digital Circuits, Electrical Engineering, Equal Employment Opportunity (EEO), Graphic Design, Low Power, Network Operations Center, Operations Research, PLL (Phase-Locked Loop), Perl Programming Language, Physical Demands, Python Programming/Scripting Language, RTL Design, Scripting (Scripting Languages), System-on-a-Chip (SoC), SystemVerilog, Tcl-Tk, Team Player, Technical/Engineering Design, Test Plan/Schedule, Testing, Timing Verification
LOCATION
Sunnyvale, CA
POSTED
4 days ago

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development.
  • Experience with digital clock control circuits, including clock dividers, glitch-free muxes, and clock gating.
  • Experience in SystemVerilog for creating microarchitecture specifications and synthesizable RTL.
  • Experience using Python, Tcl, or Perl for automating design tasks and data analysis.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • 5 years of experience with high-performance ASIC design in Phase-Locked Loop, Frequency-Locked Loop, and Delay-Locked Loop integration.
  • Experience implementing clock skipping, Dynamic Voltage and Frequency Scaling (DVFS), and fine-grained clock gating for low-power SoC optimization.
  • Knowledge of processor design or accelerators and of high-performance and low power design techniques.
  • Proficiency in Python or Perl for automating design scripts and analyzing complex clock-tree data.
  • Understanding of clock distribution challenges, including jitter, skew management, and duty-cycle distortion.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we have got to make it ourselves. Our team designs and builds the hardware, software and networking technologies that power many Google's services.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.The US base salary range for this full-time position is $138,000-$198,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

  • Work independently to create and review clock control subsystem's design micro-architecture specifications.
  • Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
  • Work with architecture and power teams to evaluate features and their impact.
  • Work with Design Validation (DV) teams to create test plans to verify, and debug design RTL.
  • Work with physical design teams to ensure design meets physical requirements and timing closure.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

About the Company

G

Google

Build for everyone

Since our founding in 1998, Google has grown by leaps and bounds. Starting from two computer science students in a university dorm room, we now have thousands of employees and offices around the world. These Googlers build products that help create opportunities for everyone, whether down the street or across the globe.

It starts with how we work together. We’re building a company where people of different views, backgrounds and experiences can do their best work and show up for one another. A place where every Googler feels like they belong.

So whether you develop new technology or creative campaigns, craft beautiful products or breakthrough partnerships, your work here is a chance to accomplish things that matter. Bring your insight, imagination, and healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.

Benefits

We strive to provide Googlers and their loved ones with a world-class benefits experience, focused on supporting their physical, financial, and emotional wellbeing. Our benefits are based on data, and centered around our users: Googlers and their families. They’re thoughtfully designed to enhance your health and wellbeing, and generous enough to make it easy for you to take good care of yourself (now, and in the future). So we can build for everyone, together.

Learn more about Google’s benefits on this site featuring Googlers’ experience.

How we Hire

Google’s hiring process is an important part of our culture. Googlers care deeply about their teams and the people who make them up. In order to  build for everyone, we know that we need a wide range of perspectives and experiences, and a fair hiring process is the first step in getting there.

Learn more about our hiring process.

COMPANY SIZE
10,000 employees or more
INDUSTRY
Computer Software
EMPLOYEE BENEFITS
Paid Sick Days, Performance Bonus, Professional Development, 401K, Stock Options, Employee Events, Retirement / Pension Plans, Tuition Reimbursement, Work From Home, Life Insurance, On Site Cafeteria
FOUNDED
1998
WEBSITE
https://goo.gle/4dbno6V

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