Verification Engineer (UVM/SystemVerilog) 5

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Verification Engineer (UVM/SystemVerilog) 5

• Location: El Segundo, California 90245
• Employment type: C2C
• Work model: On-site
• Posted August 13, 2026
• Job ID: JPC - 207799

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Job Description

Indotronix is seeking an :

Onsite Job: Verification Engineer (UVM/SystemVerilog) 5

Work Location: El Segundo, CA

Shift: First, 8:00 AM to 4:30 PM

Possible OT opportunities

Bachelor's Degree

Active Secret Clearance required to start

Required Skills

• • Engineering-minded verification engineers, not simply engineers who write test cases.

• • 7 or more years of verification 2+ UVM experience, though 5+ years is acceptable if UVM experience is solid.

• • Strong SystemVerilog and UVM experience

• • Self-checking and constrained-random verification; verification planning

• • Debugging; coverage closure

• • Active U.S. security clearance

General Recruiting Guidance

• • Across all positions, we are looking for engineers who:

• • Demonstrate strong digital hardware fundamentals.

• • Exercise sound engineering judgment.

• • Work independently with minimal oversight.

• • Communicate clearly and proactively.

• • Produce high-quality technical documentation.

• • Take ownership of their work and deliver maintainable engineering solutions.

Education / Experience:

• Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience (e.g. PhD+9 years' related work experience, Master+12 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

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Job details

Job ID JPC - 207799

Location El Segundo, California, United States

Work Model On-site

Employment Type C2C

Experience 5-7 years

Pay Rate $96.72 - $121.15 (Hourly)

Posted August 13, 2026

Skills SystemVerilog UVM verification testing debugging

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