Wireless MAC Design Engineer

Come join Apple's wireless silicon development effort, with its emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically coordinated engineering team. Develop MAC layer design for wireless communication SoCs, including creating microarchitecture and other documents based on system-level requirements, and writing area- and power-efficient RTL that is scalable. Work with systems and software teams to ensure performance and power efficiency. Collaborate with verification and emulation teams on debug, test plan review and code coverage closure. Run tools to ensure lint and CDC/RDC clean design. Work with synthesis team to review constraints, close timing and review area/timing reports.Prepare microarchitecture and RTL for digital logic of the wireless MAC based on a set of functional requirements. Ensure lint, CDC, RDC cleanliness, and work with the synthesis team on timing closure. Support verification/prototyping/emulation teams during pre-silicon verification, prototyping, and SW/FW development. Support post-silicon validation, system integration, and debug efforts and attend to any required silicon design revisions.BS in Electrical Engineering, Computer Engineering, or a related field. Excellent understanding of digital logic design fundamentals. Ability to translate functional requirements into synthesizable Verilog or SystemVerilog RTL. Knowledge of digital design flows such as RTL simulation and debug, synthesis, lint, STA, and LEC. Excellent organization skills. Excellent communication skills - both written and oral.Ability to design multi-clock-domain logic and resolve CDC problems. Experience in ASIC microarchitecture and RTL design. Understanding wireless standards, such as IEEE 802.11, 802.15, Bluetooth or 3GPP. Understanding of ASIC low power design techniques, e.g. multiple supply domains configuration and management, dynamic power/clock scaling and power analysis is a plus.