Wireless SOC Design Verification Engineer

Apple's N1 wireless chip powers connectivity across every new iPhone and its successor is already taking shape. As a Senior Wireless SOC Verification Engineer, you'll own your verification scope end-to-end on each project, from test planning through signoff. Over time, you'll grow in two directions: deeper into the IPs and subsystems you know best, or broader across different IPs and subsystems, and across levels, from block verification up to top-level SOC integration. That choice plays out project to project, not within a single one. You'll own your verification scope end-to-end, real stakes, real ownership, on a chip that ships in every new iPhone. You'll work across the Power Management Unit, the CPU subsystem, on-chip debug infrastructure, PCIe, bus fabric, boot and secure-boot sequencing, and peripherals like SPI and UART, choosing simulation, formal, or whichever approach the design actually calls for. Low-power isn't just a block, though it's part of your scope wherever it shows up: you'll verify power intent using UPF within your area, not just inside one IP. AI is already reshaping how we work. The team is pushing hard on AI-assisted verification, and you'll help figure out where it fits best whether that's test generation, debug, verification closure, or all of the above rather than inheriting a playbook someone else already wrote.Pair with design early shape the verification plan before RTL lands, not after. Debug corner-case failures and build the models coverage or proof that catch them. Verify low-power design intent using UPF within your scope. Grow into formal verification as your projects call for it. The team will help you ramp up, not expect you to arrive fluent. Own methodology decisions in your area, you set the approach, not just execute one. Verify end-to-end WiFi and Bluetooth traffic flows, from subsystem level up through top-level SOC integration. Push on AI-assisted verification, help the team find where it moves the needle. Support post-silicon bring-up when your project needs it.BS and a minimum of 10 years relevant industry experience. Proven track record of working full ASIC cycle from concept to tape-out to bring-up, including test-planning, testbench implementation, test sequence creation and debugging, and coverage closure. Expertise in SystemVerilog coding and UVM methodology.Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI-based bus architecture in UVM environment. Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC. Experience with Formal Verification. In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification. Experience taping out large SOC systems with embedded processor cores. Should be a great teammate with excellent communication and problem-solving skills and the desire to seek diverse challenges.