Job Duties: Research, design, develop, and evaluate security architectures for semiconductor and cryptographic systems; conduct comprehensive side-channel analysis (SCA) on cryptographic hardware and post-quantum cryptography (PQC) implementations to identify and mitigate vulnerabilities; architect and implement privacy-preserving machine learning frameworks utilizing homomorphic encryption for secure AI operations on GPUs; strengthen security architectures for Trusted Execution Environments (TEE) and Secure Encrypted Virtualization systems; design and implement test environments to validate Secure Memory Encryption and cryptographic components for system-on-chip (SoC) platforms, contributing to FIPS certification readiness; develop advanced side-channel attack models and countermeasures using specialized tools and custom frameworks; evaluate and optimize post-quantum cryptographic algorithms for efficiency and robustness in next-generation systems; design secure computation frameworks for machine learning accelerators and edge devices; work on problems requiring analysis and evaluation of complex security factors in hardware and software systems; utilize knowledge of cryptographic engineering, computer architecture, electronic systems, processors, and embedded security; and apply knowledge of hardware security principles, cryptanalysis techniques, and security testing methodologies to the design, development, and evaluation of AMD’s secure computing products. • Hardware security and cryptographic engineering; • Side-channel analysis (SCA) and physical attack evaluation; • Post-quantum cryptography (PQC) implementation and optimization; • Homomorphic encryption and privacy-preserving machine learning; • Secure processor architecture design; • Trusted Execution Environments (TEE) and virtualization security; • System-on-chip (SoC) security and Root of Trust (RoT) systems; • Machine learning and artificial intelligence frameworks; • Python, C/C++, and Verilog; • Security analysis tools (ChipWhisperer, Riscure Inspector); • Cryptographic hardware accelerators and coprocessors; • Secure Memory Encryption (SME) and Secure Encrypted Virtualization (SEV); • FPGA design and hardware description languages; and.