NewAssociate Digital Design Engineer BoeingAssociate Digital Design EngineerPleasanton, California$98,600–$133,400 / yearThe Boeing Company also provides eligible employees with an opportunity to enroll in a variety of benefit programs, generally including health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and a number of programs that provide for both paid and unpaid time away from work. Boeing is a Drug Free Workplace (DFW) where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies.
Design Verification Engineer (Silicon Engineering) Space Exploration TechnologiesDesign Verification Engineer (Silicon Engineering)Palo Alto, CA$135,000–$155,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan.
Sr. Soc/Asic Physical Design Engineer (Silicon Engineering) Space Exploration TechnologiesSr. Soc/Asic Physical Design Engineer (Silicon Engineering)Palo Alto, CA$175,000–$280,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan.
Sr. RTL Design Engineer RivianSr. RTL Design EngineerPalo Alto, CaliforniaFull timeRivian may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law. Rivian may share your Candidate Personal Data with (i) internal personnel who have a need to know such information in order to perform their duties, including individuals on our People Team, Finance, Legal, and the team(s) with the position(s) for which you are applying; (ii) Rivian affiliates; and (iii) Rivian’s service providers, including providers of background checks, staffing services, and cloud services.
Senior Hardware Design Engineer SambaNova Systems IncSenior Hardware Design EngineerSan Jose, CA$120,000–$200,000 / yearPowered by the intelligent SN40L chip, the SambaNova Suite is a fully integrated platform, delivered on-premises or in the cloud, combined with state-of-the-art open-source models that can be easily and securely fine-tuned using customer data for greater accuracy. SambaNova Senior Hardware Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs deployed in our AI workload acceleration systems.
NewSenior Methodologist for AIML Enhanced Design/Verification Hewlett Packard Enterprise CoSenior Methodologist for AIML Enhanced Design/VerificationSunnyvale, CA$174,000–$352,500 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
Senior Methodologist For Aiml Enhanced Design/Verification Hewlett Packard EnterpriseSenior Methodologist For Aiml Enhanced Design/VerificationSunnyvale, CA$174,000–$352,500 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
RTL / Circuit IP Design Engineer Advanced Micro Devices IncRTL / Circuit IP Design EngineerSan Jose, CATHE ROLE: The focus of this role is to plan, build, and execute the implementation of new and existing features for AMD's programmable embedded IP, resulting in final designs that meet product defined power, performance, and area targets with intended functionality that operates on silicon and is modeled accurately for customer design use. Strong understanding of circuit design concepts, translating circuit designs in an optimal way to either custom implementations or with best practices for RTL synthesis.
Design Verification Engineer RedolentDesign Verification EngineerMenlo Park, CaliforniaRole- Design Verification Engineer Location- Menlo Park, CA Minimum Qualifications BSEE/MSEE/BSCompE/MSCompE with 5 years of industry experience. Hello, One of our direct client is urgently looking for Design Verification Engineer @ Menlo Park, CA.
Digital Design/RTL/Microarchitecture RedolentDigital Design/RTL/MicroarchitectureMenlo Park, CaliforniaRole- Digital Design/RTL/Microarchitecture Location- Menlo Park, CA Minimum Qualifications BSEE/MSEE/BSCompE/MSCompE with at least 5 years of Verilog/SystemVerilog RTL experience. Hello, One of our direct client is urgently looking for Digital Design/RTL/Microarchitecture @ Menlo Park, CA.
Digital IC Design Engineer Intern NeuralinkDigital IC Design Engineer InternSouth San Francisco, CAJob Description and Responsibilities: We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces.
PMTS ASIC Digital Design IP ENGINEERING GlobalFoundries IncPMTS ASIC Digital Design IP ENGINEERINGSanta Clara, CA$167,000–$275,000 / yearSummary of Role: The PMTS Digital Design Engineer will lead the architecture implementation, microarchitecture development, and RTL design of high-performance processor cores and subsystem components. About GlobalFoundries: GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies.
Design Director (Innovation & Engineering) Turner & TownsendDesign Director (Innovation & Engineering)San Francisco, CA$150,000–$200,000 / yearThis individual will serve as a subject matter expert within the Innovation & Engineering team, partnering closely with the Vice President of Architecture to guide BOD and BTS design activities, oversee third‑party consultants, and ensure project documentation is accurate, timely, and within budget. The successful candidate will be a driven leader with strong technical expertise, excellent communication skills, and the ability to influence design strategy across a complex and fast‑growing portfolio.
Physical Design Engineer Intern, BS - Summer 2027 Marvell Technology IncPhysical Design Engineer Intern, BS - Summer 2027Santa Clara, CACompleted courses focusing on VLSI, digital logic, circuit design, computer architecture, RTL synthesis, Verilog or SystemVerilog, place and route, static timing analysis, digital systems, or microelectronics. This role is eligible to participate in Marvell''s bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company''s long-term success.
Physical Design Engineer Intern, MS - Summer 2027 Marvell Technology IncPhysical Design Engineer Intern, MS - Summer 2027Santa Clara, CACompleted courses focusing on VLSI, digital logic, circuit design, computer architecture, RTL synthesis, Verilog or SystemVerilog, place and route, static timing analysis, digital systems, or microelectronics. This role is eligible to participate in Marvell''s bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company''s long-term success.
NewEngineering Associate I (Drafter) - Project Design & Development - San Francisco Public Works (5364) City and County of San FranciscoEngineering Associate I (Drafter) - Project Design & Development - San Francisco Public Works (5364)San Francisco, CAThe staff designs and manages the construction of civic buildings and streets; cleans and greens the right of way; maintains civic buildings; manages multi-million-dollar bond programs; trains people for jobs; keeps the right of way free of hazards; paves the roads; repairs bridges and public stairways; expands accessibility; and works at the forefront addressing some of San Francisco's biggest challenges. MINIMUM QUALIFICATIONSExperience: Four (4) years of verified civil (including structural /or transportation) technical engineering drafting experience using CAD or BIM systems to prepare engineering drawings and other engineering graphic material, at least two (2) years of which must have been in a position with duties comparable to those of Class 5362 Engineering Assistant.
Job Captain (Interior Design) Northern ImpactJob Captain (Interior Design)San Francisco, CaliforniaWorks with Architectural and Interior Design team to develop the interior design solutions for projects ranging from workplace, higher education, and other community and commercial buildings. This position requires excellent design, time management, communication, and technical skills as you work closely with your team developing concepts from start to finish.
SoC Design Verification Engineer Advanced Micro Devices IncSoC Design Verification EngineerSan Jose, CAWhether you're designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger - technology that moves the world forward. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them.
Mixed-Signal Electrical Design Engineer KLA CorporationMixed-Signal Electrical Design EngineerMilpitas, CA$117,800–$172,800 / yearWe are looking for a Mixed-Signal Electrical Engineer capable of taking ownership of complex PCBAs including: designing, simulating, and validating high-performance analog, digital circuits and power supplies for our cameras! To ensure a fair and consistent evaluation, the use of AI, recording tools or other technologies to generate, suggest or provide responses during interviews-whether virtual or in person-is not permitted unless explicitly approved in advance as part of a reasonable accommodation or invited by the interviewer.
Senior Design Verification Engineer ProteanTecs Ltd.Senior Design Verification EngineerSanta Clara, CAWhy proteanTecs is a great place to work: Fast-paced and impactful: We"re a mission-driven startup, so you"ll tackle new challenges daily, wear many hats, and see your work directly influence the future of electronics. We are looking for a We are looking for a Senior Design Verification Engineer to join a global team of Application Engineers that own the technical success and customer satisfaction across multiple high-impact projects.