Sr. ASIC Design Verification Engineer (Silicon Engineering) SpaceXSr. ASIC Design Verification Engineer (Silicon Engineering)Palo Alto, CA$175,000–$280,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
Design Verification Engineer (Silicon Engineering) Space Exploration TechnologiesDesign Verification Engineer (Silicon Engineering)Palo Alto, CA$135,000–$155,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Sr. Asic Design Verification Engineer (Silicon Engineering) Space Exploration TechnologiesSr. Asic Design Verification Engineer (Silicon Engineering)Palo Alto, CA$175,000–$280,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Principal Design Verification Engineer (Silicon Engineering) SpaceXPrincipal Design Verification Engineer (Silicon Engineering)Sunnyvale, CA$210,000–$310,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
TPU SoC Design Engineer, Cloud GoogleTPU SoC Design Engineer, CloudSunnyvale, CAFull timeFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Design Verification Engineer, Silicon GoogleDesign Verification Engineer, SiliconMountain View, CAFull timeDevelop and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs using SystemVerilog Assertions (SVA). Plan the verification of complex digital design blocks by analyzing specifications and collaborating with design engineers to identify critical scenarios.
Staff Design Engineer, Digital Signal Processing GoogleStaff Design Engineer, Digital Signal ProcessingSunnyvale, CAFull timeFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Principal Design Verification Engineer (Silicon Engineering) Space Exploration TechnologiesPrincipal Design Verification Engineer (Silicon Engineering)Palo Alto, CA$210,000–$355,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
NewDFT (Design For Test) Engineer EtchedDFT (Design For Test) EngineerSan Jose, CaliforniaDevelop and implement robust Design for Test (DFT) architectures for ASIC and SoC designs to enhance test coverage, debug capability, and fault isolation. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
ASIC Design Hardware Engineer - SDC/STA (Hybrid) CiscoASIC Design Hardware Engineer - SDC/STA (Hybrid)San Jose, CaliforniaThe applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $165,000.00 - $277,600.00 Non-Metro New York state & Washington state: $146,700.00 - $247,000.00 * For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. Cisco’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.
Mixed-Signal Electrical Design Engineer KLA CorpMixed-Signal Electrical Design EngineerMilpitas, CA$117,800–$200,300 / yearWe are looking for a Mixed-Signal Electrical Engineer capable of taking ownership of complex PCBAs including: designing, simulating, and validating high-performance analog, digital circuits and power supplies for our cameras! Doctorate (Academic) Degree and 0 years related work experience; Master's Level Degree and related work experience of 3 years; Bachelor's Level Degree and related work experience of 5 years.
Analog Design Engineer, Google Cloud GoogleAnalog Design Engineer, Google CloudSunnyvale, CAFull timeFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Sunnyvale, CA, USA; Irvine, CA, USA.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
Senior Staff Analog Mixed-Signal Design Engineer Marvell Technology IncSenior Staff Analog Mixed-Signal Design EngineerSanta Clara, CAMS/PhD in Electrical Engineering and 7+ years of demonstrated experience in analog mixed-signal design, specifically in one or more of the following areas: ADC, DAC, voltage regulators, clock generation and distribution circuits, DLLs, custom high-speed digital circuits, CTLE, VGA, and TX drivers. Design and develop high-speed and low-power analog mixed-signal circuits in advanced CMOS technologies, with a focus on SerDes (Serializer/Deserializer) die-to-die communication and high-speed wireline design.
Sr. Staff Electronic Design Engineer (ADAS Hardware) Rivian Automotive IncSr. Staff Electronic Design Engineer (ADAS Hardware)Palo Alto, CA$237,000–$296,000 / yearRivian may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law. Rivian may share your Candidate Personal Data with (i) internal personnel who have a need to know such information in order to perform their duties, including individuals on our People Team, Finance, Legal, and the team(s) with the position(s) for which you are applying; (ii) Rivian affiliates; and (iii) Rivian's service providers, including providers of background checks, staffing services, and cloud services.
NewTech Lead Design Engineer Astera Labs IncTech Lead Design EngineerSan Jose, CA$133,200–$185,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
ASIC Design and Integration Engineer - Silicon Security Apple IncASIC Design and Integration Engineer - Silicon SecurityCupertino, CAYour responsibilities will include: Architecting and designing state-of-the-art security features, working closely with Platform Architecture, Design Verification to deliver high performance, area and power efficient RTL Blocks on time. In this role, you will design the state-of-the-art hardware defenses that prevent complex side channel attacks and ensure the integrity of our customers most sensitive data across Apples product line.
Senior Digital Design Engineer, IP And Methodology Astera LabsSenior Digital Design Engineer, IP And MethodologySan Jose, CA$135,000–$195,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Senior Staff Design Verification Engineer - Memory Sub-System (Lpddr/Ddr/Hbm ) MarvellSenior Staff Design Verification Engineer - Memory Sub-System (Lpddr/Ddr/Hbm )Santa Clara, CAAs part of the COE, you will design, verify, and deliver IP subsystem building blocks powering Marvell's most advanced custom chips for hyperscale cloud, AI, and data center customers - working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
Analog Design Engineer OmnivisionAnalog Design EngineerSanta Clara, California$156,853–$160,000 / yearDesign analog building blocks such as Analog Static RAM (ASRAM), ensuring support for complex readout formats including Dual Conversion Gain (DCG), Correlated Double Sampling (CDS), Correlated Multiple Sampling (CMS), and 4c2p. Requirements: Master’s degree in Electrical Engineering, Computer Engineering, or a related field with advanced-level courses work in Analog Integrated Circuit, CMOS Circuit Design, RF Circuits and Systems Design, VLSI system design, and VLSI Signal Processing.
Design Verification Engineer Cerebras SystemsDesign Verification EngineerSunnyvale, CaliforniaThis architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.